x86/ivybridge/cache.json

6         "PublicDescription": "Counts the number of lines brought into the L1 data cache.",
46         "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
53         "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
56         "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
61         "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
64         "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
69 …iption": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from…
77         "BriefDescription": "L2 cache lines filling L2",
80         "PublicDescription": "L2 cache lines filling L2.",
85         "BriefDescription": "L2 cache lines in E state filling L2",
88         "PublicDescription": "L2 cache lines in E state filling L2.",
93         "BriefDescription": "L2 cache lines in I state filling L2",
96         "PublicDescription": "L2 cache lines in I state filling L2.",
101         "BriefDescription": "L2 cache lines in S state filling L2",
104         "PublicDescription": "L2 cache lines in S state filling L2.",
109         "BriefDescription": "Clean L2 cache lines evicted by demand",
112         "PublicDescription": "Clean L2 cache lines evicted by demand.",
117         "BriefDescription": "Dirty L2 cache lines evicted by demand",
120         "PublicDescription": "Dirty L2 cache lines evicted by demand.",
125         "BriefDescription": "Dirty L2 cache lines filling the L2",
128         "PublicDescription": "Dirty L2 cache lines filling the L2.",
133         "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch",
136         "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.",
141         "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch",
144         "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.",
149         "BriefDescription": "L2 code requests",
152         "PublicDescription": "Counts all L2 code requests.",
160         "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
165         "BriefDescription": "Requests from L2 hardware prefetchers",
168         "PublicDescription": "Counts all L2 HW prefetcher requests.",
173         "BriefDescription": "RFO requests to L2 cache",
176         "PublicDescription": "Counts all L2 store RFO requests.",
181         "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
184         "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
189         "BriefDescription": "L2 cache misses when fetching instructions",
192         "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
197         "BriefDescription": "Demand Data Read requests that hit L2 cache",
200         "PublicDescription": "Demand Data Read requests that hit L2 cache.",
205         "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache",
208         "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
213         "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache",
216         "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
221         "BriefDescription": "RFO requests that hit L2 cache",
224         "PublicDescription": "RFO requests that hit L2 cache.",
229         "BriefDescription": "RFO requests that miss L2 cache",
232         "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
237         "BriefDescription": "RFOs that access cache lines in any state",
240         "PublicDescription": "RFOs that access cache lines in any state.",
245         "BriefDescription": "RFOs that hit cache lines in M state",
248         "PublicDescription": "RFOs that hit cache lines in M state.",
253         "BriefDescription": "RFOs that miss cache lines",
256         "PublicDescription": "RFOs that miss cache lines.",
261         "BriefDescription": "L2 or LLC HW prefetches that access L2 cache",
264         "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.",
269         "BriefDescription": "Transactions accessing L2 pipe",
272         "PublicDescription": "Transactions accessing L2 pipe.",
277         "BriefDescription": "L2 cache accesses when fetching instructions",
280         "PublicDescription": "L2 cache accesses when fetching instructions.",
285         "BriefDescription": "Demand Data Read requests that access L2 cache",
288         "PublicDescription": "Demand Data Read requests that access L2 cache.",
293         "BriefDescription": "L1D writebacks that access L2 cache",
296         "PublicDescription": "L1D writebacks that access L2 cache.",
301         "BriefDescription": "L2 fill requests that access L2 cache",
304         "PublicDescription": "L2 fill requests that access L2 cache.",
309         "BriefDescription": "L2 writebacks that access L2 cache",
312         "PublicDescription": "L2 writebacks that access L2 cache.",
317         "BriefDescription": "RFO requests that access L2 cache",
320         "PublicDescription": "RFO requests that access L2 cache.",
333         "BriefDescription": "Core-originated cacheable demand requests missed LLC",
336 …"PublicDescription": "This event counts each cache miss condition for references to the last level…
341         "BriefDescription": "Core-originated cacheable demand requests that refer to LLC",
344 …nt counts requests originating from the core that reference a cache line in the last level cache.",
349 …": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.",
365 …tired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.",
384 …"PublicDescription": "Retired load uops whose data source was local memory (cross-socket snoop not…
389 …ces were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not…
397         "BriefDescription": "Retired load uops with L1 cache hits as data sources.",
405         "BriefDescription": "Retired load uops which data sources following L1 data-cache miss.",
413         "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
421         "BriefDescription": "Retired load uops with L2 cache misses as data sources.",
437         "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
627 …hat hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set …
672 …hat hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set …
708 …hat hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set …
744 …hat hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set …
789 …hat hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set …
825 …hat hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set …
834 …t include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to…
843 … "Counts requests where the address of an atomic lock instruction spans a cache line boundary or t…
852         "BriefDescription": "Counts non-temporal stores",