x86/goldmontplus/cache.json

10         "BriefDescription": "L1 Cache evictions for dirty data",
13 …"PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache …
18         "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
21 …s not the same as the total number of cycles spent retrieving instruction cache lines from the mem…
29 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
33         "BriefDescription": "L2 cache request misses",
36 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
41         "BriefDescription": "L2 cache requests",
44 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
54 … loads are ignored.  A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit…
64 …cache line containing the data was in the modified state of another core or modules cache (HITM). …
69         "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)",
74         "PublicDescription": "Counts load uops retired that hit the L1 data cache.",
79         "BriefDescription": "Load uops retired that missed L1 data cache (Precise event capable)",
84         "PublicDescription": "Counts load uops retired that miss the L1 data cache.",
89         "BriefDescription": "Load uops retired that hit L2 (Precise event capable)",
94         "PublicDescription": "Counts load uops retired that hit in the L2 cache.",
99         "BriefDescription": "Load uops retired that missed L2 (Precise event capable)",
104         "PublicDescription": "Counts load uops retired that miss in the L2 cache.",
114 …cache.  Typically a load will receive this indication when some other load or prefetch missed the …
159         "BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)",
164 …ption": "Counts memory uops retired where the data requested spans a 64 byte cache line boundary.",
169         "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)",
174 …ription": "Counts load uops retired where the data requested spans a 64 byte cache line boundary.",
179         "BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)",
184 …iption": "Counts store uops retired where the data requested spans a 64 byte cache line boundary.",
206         "BriefDescription": "Counts data reads (demand & prefetch) hit the L2 cache.",
211 …"PublicDescription": "Counts data reads (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE…
216 …"BriefDescription": "Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in t…
221 …"PublicDescription": "Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in …
226 …"BriefDescription": "Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop…
231 …"PublicDescription": "Counts data reads (demand & prefetch) true miss for the L2 cache with a snoo…
236 …ata reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any res…
241 …ata reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any res…
246 …"BriefDescription": "Counts data reads generated by L1 or L2 prefetchers have any transaction resp…
251 …"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers have any transaction res…
256         "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers hit the L2 cache.",
261 …"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers hit the L2 cache. Requir…
266 …"BriefDescription": "Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a …
271 …"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a…
276 …riefDescription": "Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache …
281 …blicDescription": "Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache …
286 …tion": "Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time …
291 …tion": "Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time …
306 …data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache.",
311 …read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFF…
316 …ead, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit …
321 …ead, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit …
326 …read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss…
331 …read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss…
336 … requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any res…
341 … requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any res…
356         "BriefDescription": "Counts requests to the uncore subsystem hit the L2 cache.",
361 …"PublicDescription": "Counts requests to the uncore subsystem hit the L2 cache. Requires MSR_OFFCO…
366 …"BriefDescription": "Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in…
371 …"PublicDescription": "Counts requests to the uncore subsystem miss the L2 cache with a snoop hit i…
376 …"BriefDescription": "Counts requests to the uncore subsystem true miss for the L2 cache with a sno…
381 …"PublicDescription": "Counts requests to the uncore subsystem true miss for the L2 cache with a sn…
386 …uests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any res…
391 …uests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any res…
406 …iefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache.",
411 … "Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFF…
416 …"Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit …
421 …"Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit …
426 …eads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss…
431 …eads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss…
436 … requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any res…
441 … requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any res…
456         "BriefDescription": "Counts bus lock and split lock requests hit the L2 cache.",
461 …"PublicDescription": "Counts bus lock and split lock requests hit the L2 cache. Requires MSR_OFFCO…
466 …"BriefDescription": "Counts bus lock and split lock requests miss the L2 cache with a snoop hit in…
471 …"PublicDescription": "Counts bus lock and split lock requests miss the L2 cache with a snoop hit i…
476 …"BriefDescription": "Counts bus lock and split lock requests true miss for the L2 cache with a sno…
481 …"PublicDescription": "Counts bus lock and split lock requests true miss for the L2 cache with a sn…
486 … lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any res…
491 … lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any res…
496 …"BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache eviction…
501 …"PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictio…
506 …"Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache.",
511 …ounts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache. Re…
516 …unts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache wit…
521 …unts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache wit…
526 … the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cach…
531 … the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cach…
536 … of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the tim…
541 … of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the tim…
546 …tion": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction…
551 …tion": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction…
556 …ounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hi…
561 …ounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hi…
566 …ounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache mi…
571 …ounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache mi…
576 … demand instruction cacheline and I-side prefetch requests that miss the instruction cache true mi…
581 … demand instruction cacheline and I-side prefetch requests that miss the instruction cache true mi…
586 …struction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per …
591 …struction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per …
596 …"BriefDescription": "Counts demand cacheable data reads of full cache lines have any transaction r…
601 …"PublicDescription": "Counts demand cacheable data reads of full cache lines have any transaction …
606 …    "BriefDescription": "Counts demand cacheable data reads of full cache lines hit the L2 cache.",
611 …blicDescription": "Counts demand cacheable data reads of full cache lines hit the L2 cache. Requir…
616 …riefDescription": "Counts demand cacheable data reads of full cache lines miss the L2 cache with a…
621 …blicDescription": "Counts demand cacheable data reads of full cache lines miss the L2 cache with a…
626 …escription": "Counts demand cacheable data reads of full cache lines true miss for the L2 cache wi…
631 …escription": "Counts demand cacheable data reads of full cache lines true miss for the L2 cache wi…
636 …": "Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time o…
641 …": "Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time o…
646 …mand reads for ownership (RFO) requests generated by a write to full data cache line have any tran…
651 …mand reads for ownership (RFO) requests generated by a write to full data cache line have any tran…
656 …reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache.",
661 …for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache. Requir…
666 …or ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a …
671 …or ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a …
676 …wnership (RFO) requests generated by a write to full data cache line true miss for the L2 cache wi…
681 …wnership (RFO) requests generated by a write to full data cache line true miss for the L2 cache wi…
686 …FO) requests generated by a write to full data cache line outstanding, per cycle, from the time of…
691 …FO) requests generated by a write to full data cache line outstanding, per cycle, from the time of…
696 …Description": "Counts full cache line data writes to uncacheable write combining (USWC) memory reg…
701 …Description": "Counts full cache line data writes to uncacheable write combining (USWC) memory reg…
706 …ounts full cache line data writes to uncacheable write combining (USWC) memory region and full cac…
711 …ounts full cache line data writes to uncacheable write combining (USWC) memory region and full cac…
716 …unts full cache line data writes to uncacheable write combining (USWC) memory region and full cach…
721 …unts full cache line data writes to uncacheable write combining (USWC) memory region and full cach…
726 … full cache line data writes to uncacheable write combining (USWC) memory region and full cache-li…
731 … full cache line data writes to uncacheable write combining (USWC) memory region and full cache-li…
736 …cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non…
741 …cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non…
746 …"BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher h…
751 …"PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher …
756 …"BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher h…
761 …"PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher …
766 …"BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher m…
771 …"PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher …
776 …riefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher tru…
781 …blicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher tru…
786 …ption": "Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, …
791 …ption": "Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, …
796 …"BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher have an…
801 …"PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher have a…
806 …iption": "Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache.",
811 …tion": "Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache. Re…
816 …tion": "Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache wi…
821 …tion": "Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache wi…
826 …: "Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cach…
831 …: "Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cach…
836 …data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the ti…
841 …data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the ti…
846 …"BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher have any…
851 …"PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher have an…
856 …ription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache.",
861 …on": "Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache. Requi…
866 …on": "Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with …
871 …on": "Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with …
876 …"Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache w…
881 …"Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache w…
886 …ads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time …
891 …ads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time …
906 …": "Counts any data writes to uncacheable write combining (USWC) memory region  hit the L2 cache.",
911 …ata writes to uncacheable write combining (USWC) memory region  hit the L2 cache. Requires MSR_OFF…
916 …ta writes to uncacheable write combining (USWC) memory region  miss the L2 cache with a snoop hit …
921 …ta writes to uncacheable write combining (USWC) memory region  miss the L2 cache with a snoop hit …
926 … to uncacheable write combining (USWC) memory region  true miss for the L2 cache with a snoop miss…
931 … to uncacheable write combining (USWC) memory region  true miss for the L2 cache with a snoop miss…
936 …mbining (USWC) memory region  outstanding, per cycle, from the time of the L2 miss to when any res…
941 …mbining (USWC) memory region  outstanding, per cycle, from the time of the L2 miss to when any res…
946 …"BriefDescription": "Counts data cache lines requests by software prefetch instructions have any t…
951 …"PublicDescription": "Counts data cache lines requests by software prefetch instructions have any …
956 …"BriefDescription": "Counts data cache lines requests by software prefetch instructions hit the L2…
961 …"PublicDescription": "Counts data cache lines requests by software prefetch instructions hit the L…
966 …"BriefDescription": "Counts data cache lines requests by software prefetch instructions miss the L…
971 …"PublicDescription": "Counts data cache lines requests by software prefetch instructions miss the …
976 …"BriefDescription": "Counts data cache lines requests by software prefetch instructions true miss …
981 …"PublicDescription": "Counts data cache lines requests by software prefetch instructions true miss…
986 …scription": "Counts data cache lines requests by software prefetch instructions outstanding, per c…
991 …scription": "Counts data cache lines requests by software prefetch instructions outstanding, per c…