x86/goldmont/cache.json

10         "BriefDescription": "L1 Cache evictions for dirty data",
13 …"PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache …
18         "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
21 …s not the same as the total number of cycles spent retrieving instruction cache lines from the mem…
29 …L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the i…
33         "BriefDescription": "L2 cache request misses",
36 …"PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.",
41         "BriefDescription": "L2 cache requests",
44 …": "Counts memory requests originating from the core that reference a cache line in the L2 cache.",
54 … loads are ignored.  A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit…
64 …cache line containing the data was in the modified state of another core or modules cache (HITM). …
69         "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)",
74         "PublicDescription": "Counts load uops retired that hit the L1 data cache.",
79         "BriefDescription": "Load uops retired that missed L1 data cache (Precise event capable)",
84         "PublicDescription": "Counts load uops retired that miss the L1 data cache.",
89         "BriefDescription": "Load uops retired that hit L2 (Precise event capable)",
94         "PublicDescription": "Counts load uops retired that hit in the L2 cache.",
99         "BriefDescription": "Load uops retired that missed L2 (Precise event capable)",
104         "PublicDescription": "Counts load uops retired that miss in the L2 cache.",
114 …cache.  Typically a load will receive this indication when some other load or prefetch missed the …
159         "BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)",
164 …ption": "Counts memory uops retired where the data requested spans a 64 byte cache line boundary.",
169         "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)",
174 …ription": "Counts load uops retired where the data requested spans a 64 byte cache line boundary.",
179         "BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)",
184 …iption": "Counts store uops retired where the data requested spans a 64 byte cache line boundary.",
196         "BriefDescription": "Counts data reads (demand & prefetch) that hit the L2 cache.",
201 …"PublicDescription": "Counts data reads (demand & prefetch) that hit the L2 cache. Requires MSR_OF…
206         "BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache.",
211 …"PublicDescription": "Counts data reads (demand & prefetch) that miss the L2 cache. Requires MSR_O…
216 …"BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit…
221 …"PublicDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hi…
226 …"BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit…
231 …"PublicDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hi…
236 …"BriefDescription": "Counts data reads (demand & prefetch) that true miss for the L2 cache with a …
241 …"PublicDescription": "Counts data reads (demand & prefetch) that true miss for the L2 cache with a…
246 …  "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache.",
251 …PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache. Re…
256 … "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache.",
261 …PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache. R…
266 …"BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache wi…
271 …PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache wi…
276 …"BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache wi…
281 …PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache wi…
286 …fDescription": "Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cach…
291 …cDescription": "Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cach…
296 …read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache.",
301 … and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFF…
306 …ead, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache.",
311 …and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFF…
316 …and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit …
321 …and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit …
326 …and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit …
331 …and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit …
336 …for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss…
341 …for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss…
356         "BriefDescription": "Counts requests to the uncore subsystem that hit the L2 cache.",
361 …"PublicDescription": "Counts requests to the uncore subsystem that hit the L2 cache. Requires MSR_…
366 …"BriefDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop h…
371 …"PublicDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop …
376 …"BriefDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop h…
381 …"PublicDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop …
386 …ption": "Counts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss…
391 …ption": "Counts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss…
396 …scription": "Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache.",
401 …nts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFF…
406 …cription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache.",
411 …ts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFF…
416 …ts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit …
421 …ts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit …
426 …ts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit …
431 …ts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit …
436 …for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss…
441 …for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss…
456 …ts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache.",
461 …ts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache. …
466 …ts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache.…
471 …ts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache.…
476 …ts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache …
481 …ts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache …
486 …ts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache …
491 …ts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache …
496 …e number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 ca…
501 …e number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 ca…
506 …nts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that…
511 …nts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that…
516 …ts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that …
521 …ts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that …
526 …ts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that …
531 …ts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that …
536 …emand instruction cacheline and I-side prefetch requests that miss the instruction cache that true…
541 …emand instruction cacheline and I-side prefetch requests that miss the instruction cache that true…
546 …tion cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, …
551 …tion cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, …
556 …BriefDescription": "Counts demand cacheable data reads of full cache lines that hit the L2 cache.",
561 …icDescription": "Counts demand cacheable data reads of full cache lines that hit the L2 cache. Req…
566 …riefDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache.",
571 …cDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache. Req…
576 …fDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache with…
581 …cDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache with…
586 …fDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache with…
591 …cDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache with…
596 …cription": "Counts demand cacheable data reads of full cache lines that true miss for the L2 cache…
601 …cription": "Counts demand cacheable data reads of full cache lines that true miss for the L2 cache…
606 …ounts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the ti…
611 …ounts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the ti…
616 … for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache.",
621 … ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache. Requ…
626 …for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache.",
631 … ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache. Req…
636 … ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with…
641 … ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with…
646 … ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with…
651 … ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with…
656 …rship (RFO) requests generated by a write to full data cache line that true miss for the L2 cache …
661 …rship (RFO) requests generated by a write to full data cache line that true miss for the L2 cache …
666 …requests generated by a write to full data cache line that are outstanding, per cycle, from the ti…
671 …requests generated by a write to full data cache line that are outstanding, per cycle, from the ti…
676 …ts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-…
681 …ts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-…
686 …ts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-…
691 …ts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-…
696 …ts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-…
701 …ts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-…
706 …ts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-…
711 …ts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-…
716 …ll cache line data writes to uncacheable write combining (USWC) memory region and full cache-line …
721 …ll cache line data writes to uncacheable write combining (USWC) memory region and full cache-line …
726 …ta in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache.",
731 …e (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache. Requires MSR_OFF…
736 …scription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory re…
741 …scription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory re…
746 …cription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory reg…
751 …cription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory reg…
756 …cription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory reg…
761 …cription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory reg…
766 …cription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory reg…
771 …cription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory reg…
776 …tion": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region …
781 …tion": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region …
786 … data cache line, including the writes to uncacheable (UC) and write through (WT), and write prote…
791 … data cache line, including the writes to uncacheable (UC) and write through (WT), and write prote…
796 …"BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher t…
801 …"PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher …
806 …"BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher t…
811 …PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher t…
816 …"BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher t…
821 …PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher t…
826 …"BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher t…
831 …PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher t…
836 …efDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that …
841 …icDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that …
846 …on": "Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache.…
851 …on": "Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache.…
856 …n": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache.…
861 …n": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache.…
866 …n": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache …
871 …n": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache …
876 …n": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache …
881 …n": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache …
886 …"Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 c…
891 …"Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 c…
896 …on": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache.",
901 …": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache. Re…
906 …n": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache.",
911 …: "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache. Re…
916 …: "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache wit…
921 …: "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache wit…
926 …: "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache wit…
931 …: "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache wit…
936 …ounts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cach…
941 …ounts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cach…
946 …ounts any data writes to uncacheable write combining (USWC) memory region  that hit the L2 cache.",
951 …rites to uncacheable write combining (USWC) memory region  that hit the L2 cache. Requires MSR_OFF…
956 …unts any data writes to uncacheable write combining (USWC) memory region  that miss the L2 cache.",
961 …ites to uncacheable write combining (USWC) memory region  that miss the L2 cache. Requires MSR_OFF…
966 …"BriefDescription": "Counts data cache lines requests by software prefetch instructions that hit t…
971 …"PublicDescription": "Counts data cache lines requests by software prefetch instructions that hit …
976 …"BriefDescription": "Counts data cache lines requests by software prefetch instructions that miss …
981 …"PublicDescription": "Counts data cache lines requests by software prefetch instructions that miss…
986 …"BriefDescription": "Counts data cache lines requests by software prefetch instructions that miss …
991 …"PublicDescription": "Counts data cache lines requests by software prefetch instructions that miss…
996 …"BriefDescription": "Counts data cache lines requests by software prefetch instructions that miss …
1001 …"PublicDescription": "Counts data cache lines requests by software prefetch instructions that miss…
1006 …"BriefDescription": "Counts data cache lines requests by software prefetch instructions that true …
1011 …PublicDescription": "Counts data cache lines requests by software prefetch instructions that true …