x86/amdzen3/recommended.json

4     "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
12     "BriefDescription": "All L1 Data Cache Accesses",
17     "BriefDescription": "All L2 Cache Accesses",
24     "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30     "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
35     "BriefDescription": "L2 Cache Accesses from L2 HWPF",
41     "BriefDescription": "All L2 Cache Misses",
48     "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54     "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
59     "BriefDescription": "L2 Cache Misses from L2 Cache HWPF",
65     "BriefDescription": "All L2 Cache Hits",
72     "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
78     "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
84     "BriefDescription": "L2 Cache Hits from L2 Cache HWPF",
90     "BriefDescription": "L3 Cache Accesses",
110     "BriefDescription": "Op Cache (64B) Fetch Miss Ratio",
116     "BriefDescription": "Instruction Cache (32B) Fetch Miss Ratio",
124     "BriefDescription": "L1 Data Cache Fills: From Memory",
130     "BriefDescription": "L1 Data Cache Fills: From Remote Node",
136     "BriefDescription": "L1 Data Cache Fills: From within same CCX",
142     "BriefDescription": "L1 Data Cache Fills: From External CCX Cache",
148     "BriefDescription": "L1 Data Cache Fills: All",
160     "BriefDescription": "L2 ITLB Misses & Instruction page walks",
172     "BriefDescription": "L2 DTLB Misses & Data page walks",
183     "BriefDescription": "Macro-ops Dispatched",
196     "BriefDescription": "Macro-ops Retired"
204     "ScaleUnit": "3e-5MiB"
213     "ScaleUnit": "6.1e-5MiB"