x86/amdzen4/cache.json

5 …iption": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store all…
11 …"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for har…
17 …"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all…
23     "BriefDescription": "Demand data cache fills from local L2 cache.",
29 …"BriefDescription": "Demand data cache fills from L3 cache or different L2 cache in the same CCX.",
35 …"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in the…
41     "BriefDescription": "Demand data cache fills from either DRAM or MMIO in the same NUMA node.",
47 …"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in a d…
53 …"BriefDescription": "Demand data cache fills from either DRAM or MMIO in a different NUMA node (sa…
59     "BriefDescription": "Demand data cache fills from extension memory.",
65     "BriefDescription": "Demand data cache fills from all types of data sources.",
71     "BriefDescription": "Any data cache fills from local L2 cache.",
77     "BriefDescription": "Any data cache fills from L3 cache or different L2 cache in the same CCX.",
83 …"BriefDescription": "Any data cache fills from local L2 cache or L3 cache or different L2 cache in…
89 …"BriefDescription": "Any data cache fills from cache of another CCX when the address was in the sa…
95     "BriefDescription": "Any data cache fills from either DRAM or MMIO in the same NUMA node.",
101 …"BriefDescription": "Any data cache fills from cache of another CCX when the address was in a diff…
107 …"BriefDescription": "Any data cache fills from cache of another CCX when the address was in the sa…
113 …"BriefDescription": "Any data cache fills from either DRAM or MMIO in a different NUMA node (same …
119 …"BriefDescription": "Any data cache fills from either DRAM or MMIO in any NUMA node (same or diffe…
125 …"BriefDescription": "Any data cache fills from either cache of another CCX, DRAM or MMIO when the …
131 …"BriefDescription": "Any data cache fills from either DRAM or MMIO in any NUMA node (same or diffe…
137     "BriefDescription": "Any data cache fills from extension memory.",
143     "BriefDescription": "Any data cache fills from all types of data sources.",
149 … (move data to all cache levels), T1 (move data to all cache levels except L1) and T2 (move data t…
155 … instructions dispatched (speculative) of type PrefetchW (move data to L1 cache and mark it modifi…
161 …tched (speculative) of type PrefetchNTA (move data with minimum cache pollution i.e. non-temporal …
173 …id not fetch data outside of the processor core as the PREFETCH instruction saw a data cache hit.",
191     "BriefDescription": "Software prefetch data cache fills from local L2 cache.",
197 …"BriefDescription": "Software prefetch data cache fills from L3 cache or different L2 cache in the…
203 …"BriefDescription": "Software prefetch data cache fills from cache of another CCX in the same NUMA…
209 …"BriefDescription": "Software prefetch data cache fills from either DRAM or MMIO in the same NUMA …
215 …"BriefDescription": "Software prefetch data cache fills from cache of another CCX in a different N…
221 …"BriefDescription": "Software prefetch data cache fills from either DRAM or MMIO in a different NU…
227     "BriefDescription": "Software prefetch data cache fills from extension memory.",
233     "BriefDescription": "Software prefetch data cache fills from all types of data sources.",
239     "BriefDescription": "Hardware prefetch data cache fills from local L2 cache.",
245 …"BriefDescription": "Hardware prefetch data cache fills from L3 cache or different L2 cache in the…
251 …"BriefDescription": "Hardware prefetch data cache fills from cache of another CCX when the address…
257 …"BriefDescription": "Hardware prefetch data cache fills from either DRAM or MMIO in the same NUMA …
263 …"BriefDescription": "Hardware prefetch data cache fills from cache of another CCX when the address…
269 …"BriefDescription": "Hardware prefetch data cache fills from either DRAM or MMIO in a different NU…
275     "BriefDescription": "Hardware prefetch data cache fills from extension memory.",
281     "BriefDescription": "Hardware prefetch data cache fills from all types of data sources.",
287 …"BriefDescription": "In-flight L1 data cache misses i.e. Miss Address Buffer (MAB) allocations eac…
292 …"BriefDescription": "L2 cache requests of non-cacheable type (non-cached data and instructions rea…
298 …"BriefDescription": "L2 cache requests: from hardware prefetchers to prefetch directly into L2 (hi…
304     "BriefDescription": "L2 cache requests: prefetch directly into L2.",
310 …"BriefDescription": "L2 cache requests: data cache state change to writable, check L2 for current …
316     "BriefDescription": "L2 cache requests: instruction cache reads.",
322     "BriefDescription": "L2 cache requests: data cache shared reads.",
328     "BriefDescription": "L2 cache requests: data cache stores.",
334 …"BriefDescription": "L2 cache requests: data cache reads including hardware and software prefetch.…
340 …"BriefDescription": "L2 cache requests of common types from L1 data cache (including prefetches).",
346     "BriefDescription": "L2 cache requests of common types not including prefetches.",
352     "BriefDescription": "L2 cache requests of all types.",
358 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instructio…
364 …Description": "Core to L2 cache requests (not including L2 prefetch) with status: instruction cach…
370 …efDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instruction ca…
376 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for instruction cache h…
382 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for instruction cache a…
388 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache…
394 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instructio…
400 …iefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache st…
406 …fDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache read…
412 …iefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache re…
418 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache…
424 …  "BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data cache hits.",
430 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instructio…
436 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data cache access.",
442 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instructio…
448 …iption": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Stream (fe…
454 …fDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Next…
460 …ription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2UpDown (f…
466 …": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Burst (aggressiv…
472 …Description": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Strid…
478 …iption": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Stream (fe…
484 …Description": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Strid…
490 …Description": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Regio…
496 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of all ty…
502 …L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type …
508 …n": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of …
514 …L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type …
520 …L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type …
526 …": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of t…
532 …L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type …
538 …": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of t…
544 …": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of t…
550 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in …
556 …n": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Strea…
562 …ription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L…
568 …on": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2UpDo…
574 …L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Burst (agg…
580 …iption": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2…
586 …n": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1Strea…
592 …iption": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1…
598 …iption": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1…
604 …"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches…
610     "BriefDescription": "Instruction cache lines (64 bytes) fulfilled from the L2 cache."
615 …"BriefDescription": "Instruction cache lines (64 bytes) fulfilled from system memory or another ca…
620     "BriefDescription": "Instruction cache hits.",
626     "BriefDescription": "Instruction cache misses.",
632     "BriefDescription": "Instruction cache accesses of all types.",
638     "BriefDescription": "Op cache hits.",
644     "BriefDescription": "Op cache misses.",
650     "BriefDescription": "Op cache accesses of all types.",
656     "BriefDescription": "L3 cache misses.",
663     "BriefDescription": "L3 cache hits.",
670     "BriefDescription": "L3 cache requests for all coherent accesses.",
691 …"BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when th…
698 …"BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when th…
726     "BriefDescription": "L3 cache fill requests sourced from DRAM in the same NUMA node.",
733     "BriefDescription": "L3 cache fill requests sourced from DRAM in a different NUMA node.",
740 …"BriefDescription": "L3 cache fill requests sourced from another CCX's cache when the address was …
747 …"BriefDescription": "L3 cache fill requests sourced from another CCX's cache when the address was …
754 …"BriefDescription": "L3 cache fill requests sourced from extension memory (CXL) in the same NUMA n…
761 …"BriefDescription": "L3 cache fill requests sourced from extension memory (CXL) in a different NUM…
768     "BriefDescription": "L3 cache fill requests sourced from all data sources.",