| /openbmc/u-boot/board/freescale/t1040qds/ |
| H A D | README | 2 --------
7 ------------------
8 The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
9 processor cores with high-performance data path acceleration architecture
14 - Four e5500 cores, each with a private 256 KB L2 cache
15 - 256 KB shared L3 CoreNet platform cache (CPC)
16 - Interconnect CoreNet platform
17 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
19 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
21 - Packet parsing, classification, and distribution
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| /openbmc/u-boot/board/freescale/t208xqds/ |
| H A D | README | 1 The T2080QDS is a high-performance computing evaluation, development and
5 ------------------
6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
17 - 16 SerDes lanes up to 10.3125 GHz
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| /openbmc/u-boot/board/freescale/t208xrdb/ |
| H A D | README | 1 T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
5 ------------------
6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
17 - 16 SerDes lanes up to 10.3125 GHz
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| /openbmc/u-boot/board/freescale/t104xrdb/ |
| H A D | README | 2 --------
9 personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).
16 The board is re-designed T1040RDB board with following changes :
17 - Support of DDR4 memory and some enhancements
20 The board is re-designed T1040RDB board with following changes :
21 - Support of DDR4 memory
22 - Support for 0x86 serdes protocol which can support following interfaces
23 - 2 RGMII's on DTSEC4, DTSEC5
24 - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
27 -------------------------------------------------------------------------
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| /openbmc/u-boot/board/freescale/t102xrdb/ |
| H A D | README | 2 ------------------
4 combines two or one 64-bit Power Architecture e5500 core respectively with high
9 and general-purpose embedded computing. Its high level of integration offers
14 - two e5500 cores, each with a private 256 KB L2 cache
15 - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
16 - Three levels of instructions: User, supervisor, and hypervisor
17 - Independent boot and reset
18 - Secure boot capability
19 - 256 KB shared L3 CoreNet platform cache (CPC)
20 - Interconnect CoreNet platform
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| /openbmc/u-boot/board/freescale/t102xqds/ |
| H A D | README | 2 ------------------
4 combines two or one 64-bit Power Architecture e5500 core respectively with high
9 and general-purpose embedded computing. Its high level of integration offers
14 - two e5500 cores, each with a private 256 KB L2 cache
15 - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
16 - Three levels of instructions: User, supervisor, and hypervisor
17 - Independent boot and reset
18 - Secure boot capability
19 - 256 KB shared L3 CoreNet platform cache (CPC)
20 - Interconnect CoreNet platform
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| /openbmc/u-boot/drivers/pinctrl/ |
| H A D | pinctrl-sti.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
28 /* User-frendly defines for Pin Direction */
47 unsigned char bank; member
60 int alt = pin_desc->alt; in sti_alternate_select()
61 int bank = pin_desc->bank; in sti_alternate_select() local
62 int pin = pin_desc->pin; in sti_alternate_select()
64 sysconfreg = (unsigned long *)plat->regmap->ranges[0].start; in sti_alternate_select()
66 switch (bank) { in sti_alternate_select()
67 case 0 ... 5: /* in "SBC Bank" */ in sti_alternate_select()
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | exynos-srom.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
19 - const: samsung,exynos4210-srom
24 "#address-cells":
27 "#size-cells":
34 Reflects the memory layout with four integer values per bank. Format:
35 <bank-number> 0 <parent address of bank> <size>
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| H A D | st,stm32-fmc2-ebi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
14 - to translate AXI transactions into the appropriate external device
16 - to meet the access time requirements of the external devices
22 - Christophe Kerello <christophe.kerello@foss.st.com>
26 const: st,stm32mp1-fmc2-ebi
37 "#address-cells":
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| H A D | ti,gpmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
16 - Asynchronous SRAM-like memories and ASICs
17 - Asynchronous, synchronous, and page mode burst NOR flash
18 - NAND flash
19 - Pseudo-SRAM devices
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| /openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| H A D | gpio.txt | 1 Every GPIO controller node must have #gpio-cells property defined,
2 this information will be used to translate gpio-specifiers.
10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13 - #gpio-cells : Should be two. The first cell is the pin number and the
15 - gpio-controller : Marks the port as GPIO controller.
17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
20 - interrupts : This property provides the list of interrupt for each GPIO having
21 one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
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| /openbmc/linux/Documentation/devicetree/bindings/net/ |
| H A D | cavium-mix.txt | 4 - compatible: "cavium,octeon-5750-mix"
9 - reg: The base addresses of four separate register banks. The first
10 bank contains the MIX registers. The second bank the corresponding
11 AGL registers. The third bank are the AGL registers shared by all
12 MIX devices present. The fourth bank is the AGL_PRT_CTL shared by
15 - cell-index: A single cell specifying which portion of the shared
18 - interrupts: Two interrupt specifiers. The first is the MIX
21 - phy-handle: Optional, see ethernet.txt file in the same directory.
25 compatible = "cavium,octeon-5750-mix";
30 cell-index = <1>;
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| /openbmc/linux/Documentation/devicetree/bindings/leds/ |
| H A D | leds-lm36274.txt | 1 * Texas Instruments LM36274 4-Channel LCD Backlight Driver w/Integrated Bias
3 The LM36274 is an integrated four-channel WLED driver and LCD bias supply.
4 The backlight boost provides the power to bias four parallel LED strings with
5 up to 29V total output voltage. The 11-bit LED current is programmable via
9 Documentation/devicetree/bindings/mfd/ti-lmu.txt
12 Documentation/devicetree/bindings/regulator/lm363x-regulator.txt
15 - compatible:
16 "ti,lm36274-backlight"
17 - reg : 0
18 - #address-cells : 1
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| /openbmc/u-boot/arch/x86/include/asm/ |
| H A D | cmos_layout.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
12 * standard bank contain the RTC time and date information along with four
13 * registers, A - D, that are used for configuration of the RTC. The extended
14 * bank contains a full 128 bytes of battery backed SRAM.
16 * For simplicity in U-Boot we only support CMOS in the standard bank, and
23 * U-Boot for various reasons. It is put in such a unified place in order
|
| /openbmc/linux/drivers/mtd/maps/ |
| H A D | intel_vr_nor.c | 4 * An MTD map driver for a NOR flash bank on the Expansion Bus of the Intel
7 * The Vermilion Range Expansion Bus supports four chip selects, each of which
9 * is a 256MiB memory region containing the address spaces for all four of the
62 #define TIMING_BYTE_EN (1 << 0) /* 8-bit vs 16-bit bus */
67 mtd_device_unregister(p->info); in vr_nor_destroy_partitions()
72 /* register the flash bank */ in vr_nor_init_partitions()
73 /* partition the flash bank */ in vr_nor_init_partitions()
74 return mtd_device_register(p->info, NULL, 0); in vr_nor_init_partitions()
79 map_destroy(p->info); in vr_nor_destroy_mtd_setup()
88 for (type = probe_types; !p->info && *type; type++) in vr_nor_mtd_setup()
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| /openbmc/u-boot/board/freescale/c29xpcie/ |
| H A D | README | 3 C29XPCIE board is a series of Freescale PCIe add-in cards to perform
6 The Freescale C29x family is a high performance crypto co-processor.
12 - 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
13 - 64 Mbyte NOR flash single-chip memory
14 - 4 Gbyte NAND flash memory
15 - 1 Mbit AT24C1024 I2C EEPROM
16 - 16 Mbyte SPI memory
19 - 10/100/1000 BaseT Ethernet ports:
20 - eTSEC1, RGMII: one 10/100/1000 port
21 - eTSEC2, RGMII: one 10/100/1000 port
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| /openbmc/linux/arch/powerpc/platforms/85xx/ |
| H A D | p1022_ds.c | 42 * Board-specific initialization of the DIU. This code should probably be
77 * Note that we need to byte-swap the value before it's written to the AD
133 * obtain the upper four bits, we need to scan the LAW table. The entry which
134 * maps to the localbus will contain the upper four bits.
140 * If we only have 32-bit addressing, then the BRx address *is* the in lbc_br_to_phys()
153 /* Extract the upper four bits */ in lbc_br_to_phys()
181 guts_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts"); in p1022ds_set_monitor_port()
193 lbc_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc"); in p1022ds_set_monitor_port()
205 law_node = of_find_compatible_node(NULL, NULL, "fsl,ecm-law"); in p1022ds_set_monitor_port()
217 iprop = of_get_property(law_node, "fsl,num-laws", NULL); in p1022ds_set_monitor_port()
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| /openbmc/linux/drivers/hwspinlock/ |
| H A D | omap_hwspinlock.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2010-2021 Texas Instruments Incorporated - https://www.ti.com
8 * Hari Kanigeri <h-kanigeri2@ti.com>
9 * Ohad Ben-Cohen <ohad@wizery.com>
10 * Suman Anna <s-anna@ti.com>
40 void __iomem *lock_addr = lock->priv; in omap_hwspinlock_trylock()
48 void __iomem *lock_addr = lock->priv; in omap_hwspinlock_unlock()
77 struct device_node *node = pdev->dev.of_node; in omap_hwspinlock_probe()
78 struct hwspinlock_device *bank; in omap_hwspinlock_probe() local
86 return -ENODEV; in omap_hwspinlock_probe()
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| /openbmc/linux/drivers/gpio/ |
| H A D | gpio-realtek-otto.c | 1 // SPDX-License-Identifier: GPL-2.0-only
13 * Total register block size is 0x1C for one bank of four ports (A, B, C, D).
14 * An optional second bank, with ports E, F, G, and H, may be present, starting
42 * realtek_gpio_ctrl - Realtek Otto GPIO driver data
45 * @base: Base address of the register block for a GPIO bank
49 * @bank_read: Read a bank setting as a single 32-bit value
50 * @bank_write: Write a bank setting as a single 32-bit value
53 * The DIR, DATA, and ISR registers consist of four 8-bit port values, packed
54 * into a single 32-bit register. Use @bank_read (@bank_write) to get (assign)
55 * a value from (to) these registers. The IMR register consists of four 16-bit
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| /openbmc/linux/drivers/thermal/mediatek/ |
| H A D | auxadc_thermal.c | 1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/nvmem-consumer.h>
109 /* The number of sensing points per bank */
119 #define MT8173_TEMP_MIN -20000
198 /* The number of sensing points per bank */
219 /* The number of sensing points per bank */
258 /* The number of sensing points per bank */
276 /* The number of sensing points per bank */
472 * The MT8173 thermal controller has four banks. Each bank can read up to
473 * four temperature sensors simultaneously. The MT8173 has a total of 5
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| /openbmc/linux/arch/arm/boot/dts/ti/omap/ |
| H A D | omap-zoom-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 #include "omap-gpmc-smsc911x.dtsi"
13 * Four port TL16CP754C serial port on GPMC,
20 bank-width = <2>;
21 reg-shift = <1>;
22 reg-io-width = <1>;
23 interrupt-parent = <&gpio4>;
25 clock-frequency = <1843200>;
26 current-speed = <115200>;
27 gpmc,mux-add-data = <0>;
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/ |
| H A D | jedec,lpddr2-timings.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr2-timings
16 max-freq:
19 Maximum DDR clock frequency for the speed-bin, in Hz.
21 min-freq:
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| H A D | jedec,lpddr3-timings.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr3-timings
19 Maximum DDR clock frequency for the speed-bin, in Hz.
20 Property is deprecated, use max-freq.
23 max-freq:
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| /openbmc/u-boot/doc/ |
| H A D | README.b4860qds | 2 --------
6 -------------
7 The B4860 QorIQ Qonverge device is a Freescale high-end, multicore SoC based on
11 expanding wireless markets, such as 3GLTE (FDD and TDD), LTE-Advanced, and UMTS.
13 The B4860 is a highly-integrated StarCore and Power Architecture processor that
15 . Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
16 clusters-each core runs up to 1.2 GHz, with an architecture highly optimized for
18 . Four dual-thread e6500 Power Architecture processors organized in one cluster-each
20 . Two DDR3/3L controllers for high-speed, industry-standard memory interface each
22 . MAPLE-B3 hardware acceleration-for forward error correction schemes including
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| /openbmc/linux/Documentation/admin-guide/perf/ |
| H A D | alibaba_pmu.rst | 2 Alibaba's T-Head SoC Uncore Performance Monitoring Unit (PMU)
5 The Yitian 710, custom-built by Alibaba Group's chip development business,
6 T-Head, implements uncore PMU for performance and functional debugging to
9 DDR Sub-System Driveway (DRW) PMU Driver
12 Yitian 710 employs eight DDR5/4 channels, four on each die. Each DDR5 channel
14 channel is split into two independent sub-channels. The DDR Sub-System Driveway
15 implements separate PMUs for each sub-channel to monitor various performance
20 sub-channels of the same channel in die 0. And the PMU device of die 1 is
23 Each sub-channel has 36 PMU counters in total, which is classified into
24 four groups:
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