Lines Matching +full:four +full:- +full:bank
2 ------------------
4 combines two or one 64-bit Power Architecture e5500 core respectively with high
9 and general-purpose embedded computing. Its high level of integration offers
14 - two e5500 cores, each with a private 256 KB L2 cache
15 - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
16 - Three levels of instructions: User, supervisor, and hypervisor
17 - Independent boot and reset
18 - Secure boot capability
19 - 256 KB shared L3 CoreNet platform cache (CPC)
20 - Interconnect CoreNet platform
21 - CoreNet coherency manager supporting coherent and noncoherent transactions
23 - 150 Gbps coherent read bandwidth
24 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
25 - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
26 - Packet parsing, classification, and distribution
27 - Queue management for scheduling, packet sequencing, and congestion management
28 - Cryptography Acceleration (SEC 5.x)
29 - IEEE 1588 support
30 - Hardware buffer management for buffer allocation and deallocation
31 - MACSEC on DPAA-based Ethernet ports
32 - Ethernet interfaces
33 - Four 1 Gbps Ethernet controllers
34 - Parallel Ethernet interfaces
35 - Two RGMII interfaces
36 - High speed peripheral interfaces
37 - Three PCI Express 2.0 controllers/ports running at up to 5 GHz
38 - One SATA controller supporting 1.5 and 3.0 Gb/s operation
39 - One QSGMII interface
40 - Four SGMII interface supporting 1000 Mbps
41 - Three SGMII interfaces supporting up to 2500 Mbps
42 - 10GbE XFI or 10Base-KR interface
43 - Additional peripheral interfaces
44 - Two USB 2.0 controllers with integrated PHY
45 - SD/eSDHC/eMMC
46 - eSPI controller
47 - Four I2C controllers
48 - Four UARTs
49 - Four GPIO controllers
50 - Integrated flash controller (IFC)
51 - LCD interface (DIU) with 12 bit dual data rate
52 - Multicore programmable interrupt controller (PIC)
53 - Two 8-channel DMA engines
54 - Single source clocking implementation
55 - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
56 - QUICC Engine block
57 - 32-bit RISC controller for flexible support of the communications peripherals
58 - Serial DMA channel for receive and transmit on all serial channels
59 - Two universal communication controllers, supporting TDM, HDLC, and UART
62 ------------------
71 DDR: 64-bit 32-bit
72 IFC: 32-bit 28-bit
77 -----------------------
78 - Ethernet
79 - Two on-board 10M/100M/1G bps RGMII ethernet ports
80 - One on-board 10G bps Base-T port.
81 - DDR Memory
82 - Supports 64-bit 4GB DDR3L DIMM
83 - PCIe
84 - One on-board PCIe slot.
85 - Two on-board PCIe Mini-PCIe connectors.
86 - IFC/Local Bus
87 - NOR: 128MB 16-bit NOR Flash
88 - NAND: 1GB 8-bit NAND flash
89 - CPLD: for system controlling with programable header on-board
90 - USB
91 - Supports two USB 2.0 ports with integrated PHYs
92 - Two type A ports with 5V@1.5A per port.
93 - SDHC
94 - one SD connector supporting 1.8V/3.3V via J53.
95 - SPI
96 - On-board 64MB SPI flash
97 - Other
98 - Two Serial ports
99 - Four I2C ports
103 -----------------------
104 - T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz
105 - CoreNet fabric supporting coherent and noncoherent transactions with
107 - SDRAM memory: 2GB Micron MT40A512M8HX unbuffered 32-bit DDR4 w/o ECC
108 - Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
109 - Ethernet interfaces:
110 - one 1G RGMII port on-board(RTL8211FS PHY)
111 - one 1G SGMII port on-board(RTL8211FS PHY)
112 - one 2.5G SGMII port on-board(AQR105 PHY)
113 - PCIe: Two Mini-PCIe connectors on-board.
114 - SerDes: 4 lanes up to 10.3125GHz
115 - NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash
116 - NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash
117 - eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash.
118 - USB: one Type-A USB 2.0 port with internal PHY
119 - eSDHC: support SD/MMC and eMMC card
120 - 256Kbit M24256 I2C EEPROM
121 - RTC: Real-time clock DS1339U on I2C bus
122 - UART: one serial port on-board with RJ45 connector
123 - Debugging: JTAG/COP for T1023 debugging
127 ----------------------
129 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
130 0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
137 0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
146 -----------------------------
148 0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
149 0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
150 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
151 0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB
152 0xED300000 0xEFDFFFFF rootfs (alt bank) 44MB
153 0xED000000 0xED2FFFFF Guest image #3 (alternate bank) 3MB
154 0xECD00000 0xECFFFFFF Guest image #2 (alternate bank) 3MB
155 0xECA00000 0xECCFFFFF Guest image #1 (alternate bank) 3MB
156 0xEC900000 0xEC9FFFFF HV config device tree(alt bank) 1MB
157 0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
158 0xEC700000 0xEC7FFFFF HV.uImage (alternate bank) 1MB
159 0xEC020000 0xEC6FFFFF Linux.uImage (alt bank) ~7MB
160 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
161 0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
162 0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
163 0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
164 0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB
165 0xE9300000 0xEBDFFFFF rootfs (current bank) 44MB
166 0xE9000000 0xE92FFFFF Guest image #3 (current bank) 3MB
167 0xE8D00000 0xE8FFFFFF Guest image #2 (current bank) 3MB
168 0xE8A00000 0xE8CFFFFF Guest image #1 (current bank) 3MB
169 0xE8900000 0xE89FFFFF HV config device tree(cur bank) 1MB
170 0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
171 0xE8700000 0xE87FFFFF HV.uImage (current bank) 1MB
172 0xE8020000 0xE86FFFFF Linux.uImage (current bank) ~7MB
173 0xE8000000 0xE801FFFF RCW (current bank) 128KB
177 ---------------------------
185 ------------------------------------------
190 b. program u-boot.bin image to NOR flash
191 => tftp 1000000 u-boot.bin
201 via software: run command 'cpld reset altbank' in U-Boot.
202 via DIP-switch: set SW3[5:7] = '100'
204 via software: run command 'switch bank4' in U-Boot.
205 via DIP-switch: set SW3[5:7] = '100'
209 via software: run command 'cpld reset' in U-Boot.
210 via DIP-Switch: set SW3[5:7] = '000'
212 via software: run command 'switch bank0' in U-Boot.
213 via DIP-switch: set SW3[5:7] = '000'
219 b. program u-boot-with-spl-pbl.bin to NAND flash
220 => tftp 1000000 u-boot-with-spl-pbl.bin
229 b. program u-boot-with-spl-pbl.bin to SPI flash
230 => tftp 1000000 u-boot-with-spl-pbl.bin
243 b. program u-boot-with-spl-pbl.bin to SD/MMC card
244 => tftp 1000000 u-boot-with-spl-pbl.bin
254 2-stage NAND/SPI/SD boot loader
255 -------------------------------
256 PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
258 and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
259 Finally SPL transers control to U-Boot for futher booting.
262 - Executes within 256K
263 - No relocation required
266 -------------------------------------------------
268 -------------------------------------------------
270 -------------------------------------------------
272 -------------------------------------------------
274 -------------------------------------------------
276 -------------------------------------------------
278 -------------------------------------------------
279 |U-Boot SPL | 0xFFFD8000 (160KB) |
280 -------------------------------------------------
283 -------------------------------------------------------------
285 0x000000 0x0FFFFF U-Boot 1MB(2 block)
286 0x100000 0x17FFFF U-Boot env 512KB(1 block)
292 ----------------------------------------------------
294 0x000000 0x0FFFFF U-Boot 1MB
295 0x100000 0x15FFFF U-Boot env 8KB
300 ----------------------------------------------------
302 0x008 2048 U-Boot img 1MB
303 0x800 0016 U-Boot env 8KB
309 ----------------------------------------------------
311 0x000000 0x0FFFFF U-Boot img 1MB
312 0x100000 0x101FFF U-Boot env 8KB