1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2ba65808eSBin Meng /* 3ba65808eSBin Meng * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> 4ba65808eSBin Meng */ 5ba65808eSBin Meng 6ba65808eSBin Meng #ifndef __CMOS_LAYOUT_H 7ba65808eSBin Meng #define __CMOS_LAYOUT_H 8ba65808eSBin Meng 9ba65808eSBin Meng /* 10ba65808eSBin Meng * The RTC internal registers and RAM is organized as two banks of 128 bytes 11ba65808eSBin Meng * each, called the standard and extended banks. The first 14 bytes of the 12ba65808eSBin Meng * standard bank contain the RTC time and date information along with four 13ba65808eSBin Meng * registers, A - D, that are used for configuration of the RTC. The extended 14ba65808eSBin Meng * bank contains a full 128 bytes of battery backed SRAM. 15ba65808eSBin Meng * 16ba65808eSBin Meng * For simplicity in U-Boot we only support CMOS in the standard bank, and 17ba65808eSBin Meng * its base address starts from offset 0x10, which leaves us 112 bytes space. 18ba65808eSBin Meng */ 19ba65808eSBin Meng #define CMOS_BASE 0x10 20ba65808eSBin Meng 21ba65808eSBin Meng /* 22ba65808eSBin Meng * The file records all offsets off CMOS_BASE that is currently used by 23ba65808eSBin Meng * U-Boot for various reasons. It is put in such a unified place in order 24ba65808eSBin Meng * to be consistent across platforms. 25ba65808eSBin Meng */ 26ba65808eSBin Meng 27ba65808eSBin Meng /* stack address for S3 boot in a FSP configuration, 4 bytes */ 28ba65808eSBin Meng #define CMOS_FSP_STACK_ADDR CMOS_BASE 29ba65808eSBin Meng 30ba65808eSBin Meng #endif /* __CMOS_LAYOUT_H */ 31