4  * An MTD map driver for a NOR flash bank on the Expansion Bus of the Intel
7  * The Vermilion Range Expansion Bus supports four chip selects, each of which
9  * is a 256MiB memory region containing the address spaces for all four of the
62 #define TIMING_BYTE_EN		(1 <<  0)	/* 8-bit vs 16-bit bus */
67 	mtd_device_unregister(p->info);  in vr_nor_destroy_partitions()
72 	/* register the flash bank */  in vr_nor_init_partitions()
73 	/* partition the flash bank */  in vr_nor_init_partitions()
74 	return mtd_device_register(p->info, NULL, 0);  in vr_nor_init_partitions()
79 	map_destroy(p->info);  in vr_nor_destroy_mtd_setup()
88 	for (type = probe_types; !p->info && *type; type++)  in vr_nor_mtd_setup()
89 		p->info = do_map_probe(*type, &p->map);  in vr_nor_mtd_setup()
90 	if (!p->info)  in vr_nor_mtd_setup()
91 		return -ENODEV;  in vr_nor_mtd_setup()
93 	p->info->dev.parent = &p->dev->dev;  in vr_nor_mtd_setup()
102 	/* write-protect the flash bank */  in vr_nor_destroy_maps()
103 	exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0);  in vr_nor_destroy_maps()
105 	writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0);  in vr_nor_destroy_maps()
108 	iounmap(p->map.virt);  in vr_nor_destroy_maps()
111 	iounmap(p->csr_base);  in vr_nor_destroy_maps()
125 	csr_phys = pci_resource_start(p->dev, EXP_CSR_MBAR);  in vr_nor_init_maps()
126 	csr_len = pci_resource_len(p->dev, EXP_CSR_MBAR);  in vr_nor_init_maps()
127 	win_phys = pci_resource_start(p->dev, EXP_WIN_MBAR);  in vr_nor_init_maps()
128 	win_len = pci_resource_len(p->dev, EXP_WIN_MBAR);  in vr_nor_init_maps()
131 		return -ENODEV;  in vr_nor_init_maps()
134 		return -ENXIO;  in vr_nor_init_maps()
136 	p->csr_base = ioremap(csr_phys, csr_len);  in vr_nor_init_maps()
137 	if (!p->csr_base)  in vr_nor_init_maps()
138 		return -ENOMEM;  in vr_nor_init_maps()
140 	exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0);  in vr_nor_init_maps()
142 		dev_warn(&p->dev->dev, "Expansion Bus Chip Select 0 "  in vr_nor_init_maps()
144 		err = -ENODEV;  in vr_nor_init_maps()
148 		dev_warn(&p->dev->dev, "Expansion Bus Chip Select 0 "  in vr_nor_init_maps()
151 	p->map.name = DRV_NAME;  in vr_nor_init_maps()
152 	p->map.bankwidth = (exp_timing_cs0 & TIMING_BYTE_EN) ? 1 : 2;  in vr_nor_init_maps()
153 	p->map.phys = win_phys + CS0_START;  in vr_nor_init_maps()
154 	p->map.size = CS0_SIZE;  in vr_nor_init_maps()
155 	p->map.virt = ioremap(p->map.phys, p->map.size);  in vr_nor_init_maps()
156 	if (!p->map.virt) {  in vr_nor_init_maps()
157 		err = -ENOMEM;  in vr_nor_init_maps()
160 	simple_map_init(&p->map);  in vr_nor_init_maps()
162 	/* Enable writes to flash bank */  in vr_nor_init_maps()
164 	writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0);  in vr_nor_init_maps()
169 	iounmap(p->csr_base);  in vr_nor_init_maps()
205 	err = -ENOMEM;  in vr_nor_pci_probe()
209 	p->dev = dev;  in vr_nor_pci_probe()
228 	map_destroy(p->info);  in vr_nor_pci_probe()
231 	/* write-protect the flash bank */  in vr_nor_pci_probe()
232 	exp_timing_cs0 = readl(p->csr_base + EXP_TIMING_CS0);  in vr_nor_pci_probe()
234 	writel(exp_timing_cs0, p->csr_base + EXP_TIMING_CS0);  in vr_nor_pci_probe()
237 	iounmap(p->map.virt);  in vr_nor_pci_probe()
240 	iounmap(p->csr_base);  in vr_nor_pci_probe()