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/openbmc/docs/designs/
H A Decc-dbus-sel.md1 # ECC Error SEL for BMC
9 The IPMI SELs only define memory Error Correction Code (ECC) errors for host
12 The aim of this proposal is to record ECC events from the BMC in the IPMI System
13 Event Log (SEL). Whenever ECC occurs, the BMC generates an event with the
18 The IPMI specification defines memory system event log about ECC/other
19 correctable or ECC/other uncorrectable and whether ECC/other correctable memory
20 error logging limits are reached.[1]. The BMC ECC SEL will follow IPMI SEL
21 format and creates BMC memory ECC event log.
24 event log. It does not yet support the BMC ECC SEL feature in OpenBMC project.
25 Therefore, the memory ECC information will be registered to D-Bus and generate
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/boot-device/
H A Dboot-device-ld4.c16 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
17 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
18 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
19 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
20 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
21 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
22 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
23 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"},
24 {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"},
25 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
[all …]
H A Dboot-device-pro5.c15 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
16 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
17 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
18 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
19 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
20 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
21 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
22 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128MB, Addr 4)"},
27 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512MB, Addr 5)"},
28 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
[all …]
H A Dboot-device-pxs2.c15 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
16 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
17 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
18 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
19 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
20 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
21 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
22 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
23 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
24 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
[all …]
H A Dboot-device-ld11.c15 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
16 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
17 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
18 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
19 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
20 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
21 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
22 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
23 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
24 {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 4)"},
[all …]
H A Dboot-device-pxs3.c16 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
17 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
18 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
19 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
20 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
21 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
22 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
23 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
30 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5, BBM Last Page)"},
31 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5, BBM Last Page)"},
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Domap_gpmc.c93 * gen_true_ecc - This function will generate true ECC value, which
96 * @ecc_buf: buffer to store ecc code
98 * @return: re-formatted ECC value
107 * omap_correct_data - Compares the ecc read from nand spare area with ECC
115 * @read_ecc: ecc read from nand flash
116 * @calc_ecc: ecc read from ECC registers
127 /* Regenerate the orginal ECC */ in omap_correct_data()
130 /* Get the XOR of real ecc */ in omap_correct_data()
144 printf("Error: Ecc is wrong\n"); in omap_correct_data()
145 /* ECC itself is corrupted */ in omap_correct_data()
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H A Dfsmc_nand.c24 * ECC4 and ECC1 have 13 bytes and 3 bytes of ecc respectively for 512 bytes of
62 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118
97 * ECC placement definitions in oobfree type format
98 * There are 13 bytes of ecc for every 512 byte block and it has to be read
101 * Managing the ecc bytes in the following way makes it easier for software to
102 * read ecc bytes consecutive to data bytes. This way is similar to
196 /* The calculated ecc is actually the correction index in data */ in fsmc_bch8_correct_data()
209 * would result in an ecc error because the oob data is also in fsmc_bch8_correct_data()
210 * erased to FF and the calculated ecc for an FF data is not in fsmc_bch8_correct_data()
261 const u_char *data, u_char *ecc) in fsmc_read_hwecc() argument
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H A DKconfig15 Omit standard ECC layouts to safe space. Select this if your driver
16 is known to provide its own ECC layout.
28 bool "Atmel Hardware ECC"
32 bool "Atmel Programmable Multibit ECC (PMECC)"
36 The Programmable Multibit ECC (PMECC) controller is a programmable
40 int "PMECC Correctable ECC Bits"
44 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
59 Generate Programmable Multibit ECC (PMECC) header for SPL image.
88 of OOB area before last ECC sector data starts. This is potentially
102 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
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H A Dzynq_nand.c36 (0x1 << 6)) /* Disable ECC interrupt */
54 #define ZYNQ_NAND_ECC_CONFIG ((0x1 << 2) | /* ECC available on APB */ \
55 (0x1 << 4) | /* ECC read at end of page */ \
83 /* ECC block registers bit position and bit mask */
84 #define ZYNQ_NAND_ECC_BUSY (1 << 6) /* ECC block is busy */
85 #define ZYNQ_NAND_ECC_MASK 0x00FFFFFF /* ECC value mask */
212 /* bbt decriptors for chips with on-die ECC and
238 * zynq_nand_waitfor_ecc_completion - Wait for ECC completion
286 /* Wait till the ECC operation is complete */ in zynq_nand_init_nand_flash()
301 * zynq_nand_calculate_hwecc - Calculate Hardware ECC
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H A Dnand_bch.c3 * This file provides ECC correction for more than 1 bit per block of data,
24 * @ecclayout: private ecc layout for this BCH configuration
26 * @eccmask: XOR ecc mask, allows erased pages to be decoded as valid
36 * nand_bch_calculate_ecc - [NAND Interface] Calculate ECC for data block
39 * @code: output buffer with ECC
45 struct nand_bch_control *nbc = chip->ecc.priv; in nand_bch_calculate_ecc()
48 memset(code, 0, chip->ecc.bytes); in nand_bch_calculate_ecc()
49 encode_bch(nbc->bch, buf, chip->ecc.size, code); in nand_bch_calculate_ecc()
52 for (i = 0; i < chip->ecc.bytes; i++) in nand_bch_calculate_ecc()
62 * @read_ecc: ECC from the chip
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H A Dnand_base.c21 * if we have HW ECC support.
1134 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
1138 * @ecc: ECC buffer
1139 * @ecclen: ECC length
1144 * Check if a data buffer and its associated ECC and OOB data contains only
1151 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
1152 * different from the NAND page size. When fixing bitflips, ECC engines will
1159 * the payload data but also their associated ECC data, because a user might
1161 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
1164 * data are protected by the ECC engine.
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H A Dsunxi_nand.c212 * sunxi HW ECC infos: stores information related to HW ECC support
214 * @mode: the sunxi ECC mode field deduced from ECC requirements
215 * @layout: the OOB layout depending on the ECC requirements and the
216 * selected ECC mode
684 static u16 sunxi_nfc_randomizer_state(struct mtd_info *mtd, int page, bool ecc) in sunxi_nfc_randomizer_state() argument
692 if (ecc) { in sunxi_nfc_randomizer_state()
703 int page, bool ecc) in sunxi_nfc_randomizer_config() argument
714 state = sunxi_nfc_randomizer_state(mtd, page, ecc); in sunxi_nfc_randomizer_config()
753 bool ecc, int page) in sunxi_nfc_randomizer_write_buf() argument
755 sunxi_nfc_randomizer_config(mtd, page, ecc); in sunxi_nfc_randomizer_write_buf()
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H A Dmxc_nand.c40 /* Macros to get byte and bit positions of ECC */
48 /* OOB placement block for use with hardware ecc generation */
377 * If HW ECC is enabled, we turn it on during init. There is
390 int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
398 for (i = 0; i < chip->ecc.steps; i++) {
399 toread = min_t(int, length, chip->ecc.prepad);
405 bufpoi += chip->ecc.bytes;
406 host->col_addr += chip->ecc.bytes;
407 length -= chip->ecc.bytes;
409 toread = min_t(int, length, chip->ecc.postpad);
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H A Dlpc32xx_nand_slc.c8 * Hardware ECC support original source code
38 u32 ecc; member
44 #define CFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */
45 #define CFG_ECC_EN (1 << 3) /* ECC enable bit */
51 #define CTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */
72 /* NAND ECC Layout for small page NAND devices
88 * For Large Block: 17 descriptors = ((16 Data and ECC Read) + 1 Spare Area)
89 * For Small Block: 5 descriptors = ((4 Data and ECC Read) + 1 Spare Area)
92 static u32 ecc_buffer[8]; /* MAX ECC size */
100 * - to assign the ECC register to DMA source or destination address.
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H A Datmel_nand.c9 * Add Programmable Multibit ECC support for various AT91 SoC
30 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
71 * Return number of ecc bytes per sector according to sector size and
97 /* ECC will occupy the last ecc_len bytes continuously */ in pmecc_config_ecc_layout()
225 * Programmable Multibit ECC Control (PMECC).
436 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc, in pmecc_correct_data() argument
467 err_byte = ecc[tmp]; in pmecc_correct_data()
468 ecc[tmp] ^= (1 << bit_pos); in pmecc_correct_data()
470 pos = tmp + nand_chip->ecc.layout->eccpos[0]; in pmecc_correct_data()
472 pos, bit_pos, err_byte, ecc[tmp]); in pmecc_correct_data()
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H A Ddavinci_nand.c36 /* Definitions for 4-bit hardware ECC */
167 u_int32_t ecc = 0; in nand_davinci_readecc() local
169 ecc = __raw_readl(&(davinci_emif_regs->nandfecc[ in nand_davinci_readecc()
172 return ecc; in nand_davinci_readecc()
179 /* reading the ECC result register resets the ECC calculation */ in nand_davinci_enable_hwecc()
195 /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits in nand_davinci_calculate_ecc()
199 /* Invert so that erased block ECC is correct */ in nand_davinci_calculate_ecc()
211 * and usually shipped with U-Boot that uses software ECC: in nand_davinci_calculate_ecc()
235 if ((diff >> (12 + 3)) < this->ecc.size) { in nand_davinci_correct_data()
241 "bit ECC error at offset: %d, bit: " in nand_davinci_correct_data()
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H A Dlpc32xx_nand_mlc.c10 * The MLC NAND flash controller provides hardware Reed-Solomon ECC
12 * of-band data must be written together in order to have a valid ECC.
15 * blank (all-ones) out-of-band data and a valid ECC, and any later
16 * out-of-band data write will void the ECC.
19 * should not rely on the ECC validity.
92 * OOB data in each small page are 6 'free' then 10 ECC bytes.
95 * while the the four ECC bytes are groupe in its last 40 bytes.
97 * The struct below represents how free vs ecc oob bytes are stored
109 } ecc[4]; member
183 * @mode: mode to set the ECC HW to.
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/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Memory/
H A DMemoryECC.interface.yaml2 Implement to provide memory ECC attributes.
7 ECC logging limit reached.
11 A correctable ECC event has been detected on a read operation.
15 An uncorrectable ECC event has been detected on a read operation.
20 The state is described in ECC status.
29 There is no ECC error occurred.
32 correctable ECC detected.
35 uncorrectable ECC detected.
38 ECC logging reach limits.
/openbmc/u-boot/doc/
H A DREADME.mpc83xx.ddrecc4 The overall usage pattern for ECC diagnostic commands is the following:
18 the 'ecc testdw' 'ecc testword' command (see example 'Injecting Multiple-Bit
24 Use cases for DDR 'ecc' command:
29 => ecc captureclear
30 => ecc errdetectclr all
31 => ecc sbecnt 0
39 => ecc injectdatahi 1
43 => ecc testdw 200000 10
45 3. Check ECC status
47 => ecc status
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H A DREADME.nand52 for bad blocks or ECC errors.
84 "addr" in memory. This is a raw access, so ECC is avoided and the
106 If specified, overrides the maximum number of ECC bytes
188 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
189 and BCH16 ECC algorithms.
193 ELM controller is used for ECC error detection (not ECC calculation)
194 of BCH4, BCH8 and BCH16 ECC algorithms.
196 thus such SoC platforms need to depend on software library for ECC error
197 detection. However ECC calculation on such plaforms would still be
202 hardware ECC correction. This is useful for platforms which have ELM
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/openbmc/u-boot/fs/yaffs2/
H A Dyaffs_tagscompat.c23 /********** Tags ECC calculations *********/
33 /* Calculate an ecc */ in yaffs_calc_tags_ecc()
36 unsigned ecc = 0; in yaffs_calc_tags_ecc() local
39 tags->ecc = 0; in yaffs_calc_tags_ecc()
45 ecc ^= bit; in yaffs_calc_tags_ecc()
48 tags->ecc = ecc; in yaffs_calc_tags_ecc()
53 unsigned ecc = tags->ecc; in yaffs_check_tags_ecc() local
57 ecc ^= tags->ecc; in yaffs_check_tags_ecc()
59 if (ecc && ecc <= 64) { in yaffs_check_tags_ecc()
63 ecc--; in yaffs_check_tags_ecc()
[all …]
/openbmc/u-boot/board/ge/common/
H A Dvpd_reader.c48 size_t data_length, const u8 *ecc, size_t ecc_length) in verify_bch() argument
67 int errors = decode_bch(bch, data, data_length, ecc, NULL, NULL, in verify_bch()
80 * n-th error located in ecc (no need for data in verify_bch()
118 * | header block | data block | ... | ecc block | in vpd_reader()
122 * | id | magic | ecc | | ... | ecc | in vpd_reader()
131 * 4 byte ECC located at the end of the header block. A successful in vpd_reader()
150 /* Check that ECC header fits. */ in vpd_reader()
154 /* Validate ECC block. */ in vpd_reader()
155 u8 *ecc = &data[offset]; in vpd_reader() local
157 if (ecc[ID] != ECC_BLOCK_ID || ecc[LEN] < BLOCK_SIZE || in vpd_reader()
[all …]
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c60 u32 cur_pup, u32 pbs_pattern_idx, u32 ecc);
62 u32 pbs_pattern_idx, u32 ecc);
64 u32 *pcur_pup, u32 pbs_pattern_idx, u32 ecc);
98 u32 ecc; in ddr3_pbs_tx() local
133 /* If there is ECC, do each PBS again with mux change */ in ddr3_pbs_tx()
135 for (ecc = 0; ecc < (dram_info->ecc_ena + 1); ecc++) { in ddr3_pbs_tx()
139 * num - ecc mode dependent - 4-8 / 1 pups in ddr3_pbs_tx()
141 cur_max_pup = (1 - ecc) * in ddr3_pbs_tx()
142 dram_info->num_of_std_pups + ecc; in ddr3_pbs_tx()
144 if (ecc) { in ddr3_pbs_tx()
[all …]
/openbmc/u-boot/include/linux/mtd/
H A Drawnand.h39 * and override command or ECC setup according to flash type.
153 * Constants for Hardware ECC
155 /* Reset Hardware ECC for read */
157 /* Reset Hardware ECC for write */
159 /* Enable Hardware ECC before syndrome is read back from flash */
164 * ecc.correct() returns -EBADMSG.
356 /* Extended ECC information Block Definition (since ONFI 2.1) */
367 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
471 /* ECC and endurance block */
489 …* struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared am…
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