Lines Matching full:ecc
8 * Hardware ECC support original source code
38 u32 ecc; member
44 #define CFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */
45 #define CFG_ECC_EN (1 << 3) /* ECC enable bit */
51 #define CTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */
72 /* NAND ECC Layout for small page NAND devices
88 * For Large Block: 17 descriptors = ((16 Data and ECC Read) + 1 Spare Area)
89 * For Small Block: 5 descriptors = ((4 Data and ECC Read) + 1 Spare Area)
92 static u32 ecc_buffer[8]; /* MAX ECC size */
100 * - to assign the ECC register to DMA source or destination address.
104 #define lpc32xx_dmac_set_ecc() ((u32)&lpc32xx_nand_slc_regs->ecc)
117 /* 8-bit bus, no DMA, no ECC, ordinary CE signal */ in lpc32xx_nand_init()
176 * CTRL descriptor entry for reading ECC in lpc32xx_nand_dma_configure()
216 * 2. Copy generated ECC data from Register to Spare Area in lpc32xx_nand_dma_configure()
218 * 4. Copy generated ECC data from Register to Spare Area. in lpc32xx_nand_dma_configure()
223 * 2. Copy generated ECC data from Register to ECC calc Buffer. in lpc32xx_nand_dma_configure()
225 * 4. Copy generated ECC data from Register to ECC calc Buffer. in lpc32xx_nand_dma_configure()
231 * data & 32 bytes of ECC data. in lpc32xx_nand_dma_configure()
237 * data & 32 bytes of ECC data. in lpc32xx_nand_dma_configure()
328 /* Stop DMA & HW ECC */ in lpc32xx_nand_xfer()
334 static u32 slc_ecc_copy_to_buffer(u8 *spare, const u32 *ecc, int count) in slc_ecc_copy_to_buffer() argument
339 u32 ce = ecc[i / CONFIG_SYS_NAND_ECCBYTES]; in slc_ecc_copy_to_buffer()
356 * for doing data transfers with H/W ECC enabled.
360 /* Clear ECC */ in lpc32xx_hwecc_enable()
363 /* Setup SLC controller for H/W ECC operations */ in lpc32xx_hwecc_enable()
371 * read_ecc: ECC from the chip
372 * calc_ecc: the ECC calculated from raw data
420 uint32_t *eccpos = chip->ecc.layout->eccpos; in lpc32xx_read_page_hwecc()
427 * linked list; the ECC read is done without any software intervention. in lpc32xx_read_page_hwecc()
431 lpc32xx_dma_read_buf(mtd, p, chip->ecc.size * chip->ecc.steps); in lpc32xx_read_page_hwecc()
435 for (i = 0; i < chip->ecc.total; i++) in lpc32xx_read_page_hwecc()
438 stat = chip->ecc.correct(mtd, p, &ecc_code[0], &ecc_calc[0]); in lpc32xx_read_page_hwecc()
458 uint32_t *eccpos = chip->ecc.layout->eccpos; in lpc32xx_write_page_hwecc()
464 * linked list; the ECC read is done without any software intervention. in lpc32xx_write_page_hwecc()
468 lpc32xx_dma_write_buf(mtd, p, chip->ecc.size * chip->ecc.steps); in lpc32xx_write_page_hwecc()
471 for (i = 0; i < chip->ecc.total; i++) in lpc32xx_write_page_hwecc()
533 /* Hardware ECC calculation is supported when DMA driver is selected */ in board_nand_init()
534 lpc32xx_chip->ecc.mode = NAND_ECC_HW; in board_nand_init()
539 lpc32xx_chip->ecc.calculate = lpc32xx_ecc_calculate; in board_nand_init()
540 lpc32xx_chip->ecc.correct = lpc32xx_correct_data; in board_nand_init()
541 lpc32xx_chip->ecc.hwctl = lpc32xx_hwecc_enable; in board_nand_init()
544 lpc32xx_chip->ecc.read_page = lpc32xx_read_page_hwecc; in board_nand_init()
545 lpc32xx_chip->ecc.write_page = lpc32xx_write_page_hwecc; in board_nand_init()
549 * Hardware ECC calculation is not supported by the driver, in board_nand_init()
553 lpc32xx_chip->ecc.mode = NAND_ECC_SOFT; in board_nand_init()
568 lpc32xx_chip->ecc.size = CONFIG_SYS_NAND_ECCSIZE; in board_nand_init()
569 lpc32xx_chip->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; in board_nand_init()
570 lpc32xx_chip->ecc.strength = 1; in board_nand_init()
573 lpc32xx_chip->ecc.layout = &lpc32xx_nand_oob_16; in board_nand_init()