Lines Matching full:ecc
60 u32 cur_pup, u32 pbs_pattern_idx, u32 ecc);
62 u32 pbs_pattern_idx, u32 ecc);
64 u32 *pcur_pup, u32 pbs_pattern_idx, u32 ecc);
98 u32 ecc; in ddr3_pbs_tx() local
133 /* If there is ECC, do each PBS again with mux change */ in ddr3_pbs_tx()
135 for (ecc = 0; ecc < (dram_info->ecc_ena + 1); ecc++) { in ddr3_pbs_tx()
139 * num - ecc mode dependent - 4-8 / 1 pups in ddr3_pbs_tx()
141 cur_max_pup = (1 - ecc) * in ddr3_pbs_tx()
142 dram_info->num_of_std_pups + ecc; in ddr3_pbs_tx()
144 if (ecc) { in ddr3_pbs_tx()
158 /* ECC Support - Switch ECC Mux on ecc=1 */ in ddr3_pbs_tx()
161 reg |= (dram_info->ecc_ena * ecc << in ddr3_pbs_tx()
165 if (ecc) in ddr3_pbs_tx()
166 DEBUG_PBS_S("DDR3 - PBS Tx - ECC Mux Enabled\n"); in ddr3_pbs_tx()
168 DEBUG_PBS_S("DDR3 - PBS Tx - ECC Mux Disabled\n"); in ddr3_pbs_tx()
175 pup + ecc * in ddr3_pbs_tx()
204 (1 - ecc) + in ddr3_pbs_tx()
205 ecc * ECC_PUP] in ddr3_pbs_tx()
206 [dq], CS0, (1 - ecc) * in ddr3_pbs_tx()
207 PUP_BC + ecc * ECC_PUP, 0, in ddr3_pbs_tx()
219 ecc)) in ddr3_pbs_tx()
230 &cur_pup, pattern_idx, ecc)) in ddr3_pbs_tx()
250 DEBUG_PBS_D((pup + (ecc * ECC_PUP)), 1); in ddr3_pbs_tx()
278 skew_sum_array[pup + (ecc * (max_pup - 1))] in ddr3_pbs_tx()
284 /* ECC Support - Disable ECC MUX */ in ddr3_pbs_tx()
324 * FOR ECC only :: found min and max value for current in ddr3_pbs_tx()
406 u32 pbs_pattern_idx, u32 ecc) in ddr3_tx_shift_dqs_adll_step_before_fail() argument
435 if (cur_pup == 0x1) /* Ecc mode */ in ddr3_tx_shift_dqs_adll_step_before_fail()
453 pup * (1 - ecc) + in ddr3_tx_shift_dqs_adll_step_before_fail()
454 ECC_PUP * ecc, adll_val); in ddr3_tx_shift_dqs_adll_step_before_fail()
505 ddr3_pbs_write_pup_dqs_reg(CS0, pup * (1 - ecc) + ECC_PUP * ecc, in ddr3_tx_shift_dqs_adll_step_before_fail()
540 u32 ecc; in ddr3_pbs_rx() local
576 /* If there is ECC, do each PBS again with mux change */ in ddr3_pbs_rx()
578 for (ecc = 0; ecc < (dram_info->ecc_ena + 1); ecc++) { in ddr3_pbs_rx()
581 * num - ecc mode dependent - 4-8 / 1 pups in ddr3_pbs_rx()
583 cur_max_pup = (1 - ecc) * in ddr3_pbs_rx()
584 dram_info->num_of_std_pups + ecc; in ddr3_pbs_rx()
586 if (ecc) { in ddr3_pbs_rx()
600 /* ECC Support - Switch ECC Mux on ecc=1 */ in ddr3_pbs_rx()
603 reg |= (dram_info->ecc_ena * ecc << in ddr3_pbs_rx()
607 if (ecc) in ddr3_pbs_rx()
608 DEBUG_PBS_FULL_S("DDR3 - PBS Rx - ECC Mux Enabled\n"); in ddr3_pbs_rx()
610 DEBUG_PBS_FULL_S("DDR3 - PBS Rx - ECC Mux Disabled\n"); in ddr3_pbs_rx()
617 pup + ecc * (max_pup - 1)][dq] = in ddr3_pbs_rx()
644 pup * (1 - ecc) in ddr3_pbs_rx()
645 + ecc * ECC_PUP] in ddr3_pbs_rx()
647 pup + ecc * ECC_PUP, in ddr3_pbs_rx()
656 ecc * in ddr3_pbs_rx()
666 pattern_idx, ecc); in ddr3_pbs_rx()
703 (ecc * ECC_PUP), 0, in ddr3_pbs_rx()
715 [pup * (1 - ecc) + in ddr3_pbs_rx()
716 ecc * ECC_PUP] in ddr3_pbs_rx()
718 pup + ecc * ECC_PUP, in ddr3_pbs_rx()
731 pattern_idx, ecc)) { in ddr3_pbs_rx()
749 pup + ecc * ECC_PUP, in ddr3_pbs_rx()
761 (ecc * ECC_PUP)), 1); in ddr3_pbs_rx()
791 [pup + (ecc * (max_pup - 1))] in ddr3_pbs_rx()
797 /* ECC Support - Disable ECC MUX */ in ddr3_pbs_rx()
812 * FOR ECC only :: found min and max value for in ddr3_pbs_rx()
917 u32 pbs_pattern_idx, u32 ecc) in ddr3_rx_shift_dqs_to_first_fail() argument
946 if (cur_pup == 0x1) /* Ecc mode */ in ddr3_rx_shift_dqs_to_first_fail()
958 ddr3_write_pup_reg(PUP_DQS_RD, CS0, pup + ecc * ECC_PUP, 0, in ddr3_rx_shift_dqs_to_first_fail()
983 ddr3_write_pup_reg(PUP_DQS_RD, CS0, pup + ecc * ECC_PUP, in ddr3_rx_shift_dqs_to_first_fail()
1011 pup + ecc * ECC_PUP, 0, in ddr3_rx_shift_dqs_to_first_fail()
1047 pup + ecc * ECC_PUP, 0, in ddr3_rx_shift_dqs_to_first_fail()
1073 pup + ecc * ECC_PUP, 0, in ddr3_rx_shift_dqs_to_first_fail()
1087 u32 pbs_curr_val, u32 start_pbs, u32 ecc, int is_tx) in lock_pups() argument
1097 idx = pup * (1 - ecc) + ecc * ECC_PUP; in lock_pups()
1137 u32 *pcur_pup, u32 pbs_pattern_idx, u32 ecc) in ddr3_pbs_per_bit() argument
1188 if (pup_locked == 0x1) /* Ecc mode */ in ddr3_pbs_per_bit()
1213 idx = pup * (1 - ecc) + ecc * ECC_PUP; in ddr3_pbs_per_bit()
1245 [pbs_cmp_retry], ecc)) in ddr3_pbs_per_bit()
1399 start_pbs, ecc, is_tx); in ddr3_pbs_per_bit()