36 /* Definitions for 4-bit hardware ECC */
167 	u_int32_t	ecc = 0;  in nand_davinci_readecc()  local
169 	ecc = __raw_readl(&(davinci_emif_regs->nandfecc[  in nand_davinci_readecc()
172 	return ecc;  in nand_davinci_readecc()
179 	/* reading the ECC result register resets the ECC calculation */  in nand_davinci_enable_hwecc()
195 	/* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits  in nand_davinci_calculate_ecc()
199 	/* Invert so that erased block ECC is correct */  in nand_davinci_calculate_ecc()
211 	 * and usually shipped with U-Boot that uses software ECC:  in nand_davinci_calculate_ecc()
235 			if ((diff >> (12 + 3)) < this->ecc.size) {  in nand_davinci_correct_data()
241 					 "bit ECC error at offset: %d, bit: "  in nand_davinci_correct_data()
248 			/* Single bit ECC error in the ECC itself,  in nand_davinci_correct_data()
250 			pr_debug("Single bit ECC error in " "ECC.\n");  in nand_davinci_correct_data()
254 			pr_debug("ECC UNCORRECTED_ERROR 1\n");  in nand_davinci_correct_data()
371 	/* save current ECC layout and assign Keystone RBL ECC layout */  in nand_davinci_write_page()
373 		saved_ecc_layout = chip->ecc.layout;  in nand_davinci_write_page()
374 		chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;  in nand_davinci_write_page()
375 		mtd->oobavail = chip->ecc.layout->oobavail;  in nand_davinci_write_page()
381 		status = chip->ecc.write_page_raw(mtd, chip, buf,  in nand_davinci_write_page()
384 		status = chip->ecc.write_page(mtd, chip, buf,  in nand_davinci_write_page()
402 	/* restore ECC layout */  in nand_davinci_write_page()
404 		chip->ecc.layout = saved_ecc_layout;  in nand_davinci_write_page()
412  * nand_davinci_read_page_hwecc - hardware ECC based page read function
419  * Not for syndrome calculating ECC controllers which need a special oob layout.
424 	int i, eccsize = chip->ecc.size;  in nand_davinci_read_page_hwecc()
425 	int eccbytes = chip->ecc.bytes;  in nand_davinci_read_page_hwecc()
426 	int eccsteps = chip->ecc.steps;  in nand_davinci_read_page_hwecc()
431 	struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout;  in nand_davinci_read_page_hwecc()
433 	/* save current ECC layout and assign Keystone RBL ECC layout */  in nand_davinci_read_page_hwecc()
435 		chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;  in nand_davinci_read_page_hwecc()
436 		mtd->oobavail = chip->ecc.layout->oobavail;  in nand_davinci_read_page_hwecc()
439 	eccpos = chip->ecc.layout->eccpos;  in nand_davinci_read_page_hwecc()
446 	for (i = 0; i < chip->ecc.total; i++)  in nand_davinci_read_page_hwecc()
452 		chip->ecc.hwctl(mtd, NAND_ECC_READ);  in nand_davinci_read_page_hwecc()
454 		chip->ecc.calculate(mtd, p, &ecc_calc[i]);  in nand_davinci_read_page_hwecc()
456 		stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);  in nand_davinci_read_page_hwecc()
463 	/* restore ECC layout */  in nand_davinci_read_page_hwecc()
465 		chip->ecc.layout = saved_ecc_layout;  in nand_davinci_read_page_hwecc()
481 		 * Start a new ECC calculation for reading or writing 512 bytes  in nand_davinci_4bit_enable_hwecc()
499 static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])  in nand_davinci_4bit_readecc()
504 		ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) &  in nand_davinci_4bit_readecc()
520 	/*Convert 10 bit ecc value to 8 bit */  in nand_davinci_4bit_calculate_ecc()
568 	 * Check for an ECC where all bytes are 0xFF.  If this is the case, we  in nand_davinci_4bit_correct_data()
570 	 * the ECC.  in nand_davinci_4bit_correct_data()
583 	 * Write the parity values in the NAND Flash 4-bit ECC Load register.  in nand_davinci_4bit_correct_data()
623 	 * writing the ECC values in previous step.  in nand_davinci_4bit_correct_data()
629 	 * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.  in nand_davinci_4bit_correct_data()
654 	 * Otherwise ECC calculation has not even begun and the next loop might  in nand_davinci_4bit_correct_data()
783 	nand->ecc.read_page = nand_davinci_read_page_hwecc;  in davinci_nand_init()
796 	nand->ecc.mode = NAND_ECC_HW;  in davinci_nand_init()
797 	nand->ecc.size = 512;  in davinci_nand_init()
798 	nand->ecc.bytes = 3;  in davinci_nand_init()
799 	nand->ecc.strength = 1;  in davinci_nand_init()
800 	nand->ecc.calculate = nand_davinci_calculate_ecc;  in davinci_nand_init()
801 	nand->ecc.correct  = nand_davinci_correct_data;  in davinci_nand_init()
802 	nand->ecc.hwctl  = nand_davinci_enable_hwecc;  in davinci_nand_init()
804 	nand->ecc.mode = NAND_ECC_SOFT;  in davinci_nand_init()
807 	nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;  in davinci_nand_init()
808 	nand->ecc.size = 512;  in davinci_nand_init()
809 	nand->ecc.bytes = 10;  in davinci_nand_init()
810 	nand->ecc.strength = 4;  in davinci_nand_init()
811 	nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;  in davinci_nand_init()
812 	nand->ecc.correct = nand_davinci_4bit_correct_data;  in davinci_nand_init()
813 	nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;  in davinci_nand_init()
814 	nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;  in davinci_nand_init()