Lines Matching full:ecc
52 for bad blocks or ECC errors.
84 "addr" in memory. This is a raw access, so ECC is avoided and the
106 If specified, overrides the maximum number of ECC bytes
188 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
189 and BCH16 ECC algorithms.
193 ELM controller is used for ECC error detection (not ECC calculation)
194 of BCH4, BCH8 and BCH16 ECC algorithms.
196 thus such SoC platforms need to depend on software library for ECC error
197 detection. However ECC calculation on such plaforms would still be
202 hardware ECC correction. This is useful for platforms which have ELM
206 SPL-NAND driver with software ECC correction support.
209 On OMAP platforms, this CONFIG specifies NAND ECC scheme.
223 - ecc calculation using GPMC hardware engine,
229 - ecc calculation using GPMC hardware engine,
233 - ecc calculation using GPMC hardware engine,
236 How to select ECC scheme on OMAP and AMxx platforms ?
238 Though higher ECC schemes have more capability to detect and correct
239 bit-flips, but still selection of ECC scheme is dependent on following
242 SoC cannot support BCHx_HW ECC schemes.
244 With higher ECC schemes, more OOB/Spare area is required to
245 store ECC. So choice of ECC scheme is limited by NAND oobsize.
253 ECC_BYTES = number of ECC bytes generated to
255 3 for HAM1_xx ecc schemes
256 7 for BCH4_xx ecc schemes
257 14 for BCH8_xx ecc schemes
258 26 for BCH16_xx ecc schemes