1*a430fa06SMiquel Raynal // SPDX-License-Identifier: GPL-2.0+
2*a430fa06SMiquel Raynal /*
3*a430fa06SMiquel Raynal * NAND driver for TI DaVinci based boards.
4*a430fa06SMiquel Raynal *
5*a430fa06SMiquel Raynal * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6*a430fa06SMiquel Raynal *
7*a430fa06SMiquel Raynal * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
8*a430fa06SMiquel Raynal */
9*a430fa06SMiquel Raynal
10*a430fa06SMiquel Raynal /*
11*a430fa06SMiquel Raynal *
12*a430fa06SMiquel Raynal * linux/drivers/mtd/nand/raw/nand_davinci.c
13*a430fa06SMiquel Raynal *
14*a430fa06SMiquel Raynal * NAND Flash Driver
15*a430fa06SMiquel Raynal *
16*a430fa06SMiquel Raynal * Copyright (C) 2006 Texas Instruments.
17*a430fa06SMiquel Raynal *
18*a430fa06SMiquel Raynal * ----------------------------------------------------------------------------
19*a430fa06SMiquel Raynal *
20*a430fa06SMiquel Raynal * ----------------------------------------------------------------------------
21*a430fa06SMiquel Raynal *
22*a430fa06SMiquel Raynal * Overview:
23*a430fa06SMiquel Raynal * This is a device driver for the NAND flash device found on the
24*a430fa06SMiquel Raynal * DaVinci board which utilizes the Samsung k9k2g08 part.
25*a430fa06SMiquel Raynal *
26*a430fa06SMiquel Raynal Modifications:
27*a430fa06SMiquel Raynal ver. 1.0: Feb 2005, Vinod/Sudhakar
28*a430fa06SMiquel Raynal -
29*a430fa06SMiquel Raynal */
30*a430fa06SMiquel Raynal
31*a430fa06SMiquel Raynal #include <common.h>
32*a430fa06SMiquel Raynal #include <asm/io.h>
33*a430fa06SMiquel Raynal #include <nand.h>
34*a430fa06SMiquel Raynal #include <asm/ti-common/davinci_nand.h>
35*a430fa06SMiquel Raynal
36*a430fa06SMiquel Raynal /* Definitions for 4-bit hardware ECC */
37*a430fa06SMiquel Raynal #define NAND_TIMEOUT 10240
38*a430fa06SMiquel Raynal #define NAND_ECC_BUSY 0xC
39*a430fa06SMiquel Raynal #define NAND_4BITECC_MASK 0x03FF03FF
40*a430fa06SMiquel Raynal #define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
41*a430fa06SMiquel Raynal #define ECC_STATE_NO_ERR 0x0
42*a430fa06SMiquel Raynal #define ECC_STATE_TOO_MANY_ERRS 0x1
43*a430fa06SMiquel Raynal #define ECC_STATE_ERR_CORR_COMP_P 0x2
44*a430fa06SMiquel Raynal #define ECC_STATE_ERR_CORR_COMP_N 0x3
45*a430fa06SMiquel Raynal
46*a430fa06SMiquel Raynal /*
47*a430fa06SMiquel Raynal * Exploit the little endianness of the ARM to do multi-byte transfers
48*a430fa06SMiquel Raynal * per device read. This can perform over twice as quickly as individual
49*a430fa06SMiquel Raynal * byte transfers when buffer alignment is conducive.
50*a430fa06SMiquel Raynal *
51*a430fa06SMiquel Raynal * NOTE: This only works if the NAND is not connected to the 2 LSBs of
52*a430fa06SMiquel Raynal * the address bus. On Davinci EVM platforms this has always been true.
53*a430fa06SMiquel Raynal */
nand_davinci_read_buf(struct mtd_info * mtd,uint8_t * buf,int len)54*a430fa06SMiquel Raynal static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
55*a430fa06SMiquel Raynal {
56*a430fa06SMiquel Raynal struct nand_chip *chip = mtd_to_nand(mtd);
57*a430fa06SMiquel Raynal const u32 *nand = chip->IO_ADDR_R;
58*a430fa06SMiquel Raynal
59*a430fa06SMiquel Raynal /* Make sure that buf is 32 bit aligned */
60*a430fa06SMiquel Raynal if (((int)buf & 0x3) != 0) {
61*a430fa06SMiquel Raynal if (((int)buf & 0x1) != 0) {
62*a430fa06SMiquel Raynal if (len) {
63*a430fa06SMiquel Raynal *buf = readb(nand);
64*a430fa06SMiquel Raynal buf += 1;
65*a430fa06SMiquel Raynal len--;
66*a430fa06SMiquel Raynal }
67*a430fa06SMiquel Raynal }
68*a430fa06SMiquel Raynal
69*a430fa06SMiquel Raynal if (((int)buf & 0x3) != 0) {
70*a430fa06SMiquel Raynal if (len >= 2) {
71*a430fa06SMiquel Raynal *(u16 *)buf = readw(nand);
72*a430fa06SMiquel Raynal buf += 2;
73*a430fa06SMiquel Raynal len -= 2;
74*a430fa06SMiquel Raynal }
75*a430fa06SMiquel Raynal }
76*a430fa06SMiquel Raynal }
77*a430fa06SMiquel Raynal
78*a430fa06SMiquel Raynal /* copy aligned data */
79*a430fa06SMiquel Raynal while (len >= 4) {
80*a430fa06SMiquel Raynal *(u32 *)buf = __raw_readl(nand);
81*a430fa06SMiquel Raynal buf += 4;
82*a430fa06SMiquel Raynal len -= 4;
83*a430fa06SMiquel Raynal }
84*a430fa06SMiquel Raynal
85*a430fa06SMiquel Raynal /* mop up any remaining bytes */
86*a430fa06SMiquel Raynal if (len) {
87*a430fa06SMiquel Raynal if (len >= 2) {
88*a430fa06SMiquel Raynal *(u16 *)buf = readw(nand);
89*a430fa06SMiquel Raynal buf += 2;
90*a430fa06SMiquel Raynal len -= 2;
91*a430fa06SMiquel Raynal }
92*a430fa06SMiquel Raynal
93*a430fa06SMiquel Raynal if (len)
94*a430fa06SMiquel Raynal *buf = readb(nand);
95*a430fa06SMiquel Raynal }
96*a430fa06SMiquel Raynal }
97*a430fa06SMiquel Raynal
nand_davinci_write_buf(struct mtd_info * mtd,const uint8_t * buf,int len)98*a430fa06SMiquel Raynal static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
99*a430fa06SMiquel Raynal int len)
100*a430fa06SMiquel Raynal {
101*a430fa06SMiquel Raynal struct nand_chip *chip = mtd_to_nand(mtd);
102*a430fa06SMiquel Raynal const u32 *nand = chip->IO_ADDR_W;
103*a430fa06SMiquel Raynal
104*a430fa06SMiquel Raynal /* Make sure that buf is 32 bit aligned */
105*a430fa06SMiquel Raynal if (((int)buf & 0x3) != 0) {
106*a430fa06SMiquel Raynal if (((int)buf & 0x1) != 0) {
107*a430fa06SMiquel Raynal if (len) {
108*a430fa06SMiquel Raynal writeb(*buf, nand);
109*a430fa06SMiquel Raynal buf += 1;
110*a430fa06SMiquel Raynal len--;
111*a430fa06SMiquel Raynal }
112*a430fa06SMiquel Raynal }
113*a430fa06SMiquel Raynal
114*a430fa06SMiquel Raynal if (((int)buf & 0x3) != 0) {
115*a430fa06SMiquel Raynal if (len >= 2) {
116*a430fa06SMiquel Raynal writew(*(u16 *)buf, nand);
117*a430fa06SMiquel Raynal buf += 2;
118*a430fa06SMiquel Raynal len -= 2;
119*a430fa06SMiquel Raynal }
120*a430fa06SMiquel Raynal }
121*a430fa06SMiquel Raynal }
122*a430fa06SMiquel Raynal
123*a430fa06SMiquel Raynal /* copy aligned data */
124*a430fa06SMiquel Raynal while (len >= 4) {
125*a430fa06SMiquel Raynal __raw_writel(*(u32 *)buf, nand);
126*a430fa06SMiquel Raynal buf += 4;
127*a430fa06SMiquel Raynal len -= 4;
128*a430fa06SMiquel Raynal }
129*a430fa06SMiquel Raynal
130*a430fa06SMiquel Raynal /* mop up any remaining bytes */
131*a430fa06SMiquel Raynal if (len) {
132*a430fa06SMiquel Raynal if (len >= 2) {
133*a430fa06SMiquel Raynal writew(*(u16 *)buf, nand);
134*a430fa06SMiquel Raynal buf += 2;
135*a430fa06SMiquel Raynal len -= 2;
136*a430fa06SMiquel Raynal }
137*a430fa06SMiquel Raynal
138*a430fa06SMiquel Raynal if (len)
139*a430fa06SMiquel Raynal writeb(*buf, nand);
140*a430fa06SMiquel Raynal }
141*a430fa06SMiquel Raynal }
142*a430fa06SMiquel Raynal
nand_davinci_hwcontrol(struct mtd_info * mtd,int cmd,unsigned int ctrl)143*a430fa06SMiquel Raynal static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
144*a430fa06SMiquel Raynal unsigned int ctrl)
145*a430fa06SMiquel Raynal {
146*a430fa06SMiquel Raynal struct nand_chip *this = mtd_to_nand(mtd);
147*a430fa06SMiquel Raynal u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
148*a430fa06SMiquel Raynal
149*a430fa06SMiquel Raynal if (ctrl & NAND_CTRL_CHANGE) {
150*a430fa06SMiquel Raynal IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
151*a430fa06SMiquel Raynal
152*a430fa06SMiquel Raynal if (ctrl & NAND_CLE)
153*a430fa06SMiquel Raynal IO_ADDR_W |= MASK_CLE;
154*a430fa06SMiquel Raynal if (ctrl & NAND_ALE)
155*a430fa06SMiquel Raynal IO_ADDR_W |= MASK_ALE;
156*a430fa06SMiquel Raynal this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
157*a430fa06SMiquel Raynal }
158*a430fa06SMiquel Raynal
159*a430fa06SMiquel Raynal if (cmd != NAND_CMD_NONE)
160*a430fa06SMiquel Raynal writeb(cmd, IO_ADDR_W);
161*a430fa06SMiquel Raynal }
162*a430fa06SMiquel Raynal
163*a430fa06SMiquel Raynal #ifdef CONFIG_SYS_NAND_HW_ECC
164*a430fa06SMiquel Raynal
nand_davinci_readecc(struct mtd_info * mtd)165*a430fa06SMiquel Raynal static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
166*a430fa06SMiquel Raynal {
167*a430fa06SMiquel Raynal u_int32_t ecc = 0;
168*a430fa06SMiquel Raynal
169*a430fa06SMiquel Raynal ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
170*a430fa06SMiquel Raynal CONFIG_SYS_NAND_CS - 2]));
171*a430fa06SMiquel Raynal
172*a430fa06SMiquel Raynal return ecc;
173*a430fa06SMiquel Raynal }
174*a430fa06SMiquel Raynal
nand_davinci_enable_hwecc(struct mtd_info * mtd,int mode)175*a430fa06SMiquel Raynal static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
176*a430fa06SMiquel Raynal {
177*a430fa06SMiquel Raynal u_int32_t val;
178*a430fa06SMiquel Raynal
179*a430fa06SMiquel Raynal /* reading the ECC result register resets the ECC calculation */
180*a430fa06SMiquel Raynal nand_davinci_readecc(mtd);
181*a430fa06SMiquel Raynal
182*a430fa06SMiquel Raynal val = __raw_readl(&davinci_emif_regs->nandfcr);
183*a430fa06SMiquel Raynal val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
184*a430fa06SMiquel Raynal val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
185*a430fa06SMiquel Raynal __raw_writel(val, &davinci_emif_regs->nandfcr);
186*a430fa06SMiquel Raynal }
187*a430fa06SMiquel Raynal
nand_davinci_calculate_ecc(struct mtd_info * mtd,const u_char * dat,u_char * ecc_code)188*a430fa06SMiquel Raynal static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
189*a430fa06SMiquel Raynal u_char *ecc_code)
190*a430fa06SMiquel Raynal {
191*a430fa06SMiquel Raynal u_int32_t tmp;
192*a430fa06SMiquel Raynal
193*a430fa06SMiquel Raynal tmp = nand_davinci_readecc(mtd);
194*a430fa06SMiquel Raynal
195*a430fa06SMiquel Raynal /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
196*a430fa06SMiquel Raynal * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
197*a430fa06SMiquel Raynal tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
198*a430fa06SMiquel Raynal
199*a430fa06SMiquel Raynal /* Invert so that erased block ECC is correct */
200*a430fa06SMiquel Raynal tmp = ~tmp;
201*a430fa06SMiquel Raynal
202*a430fa06SMiquel Raynal *ecc_code++ = tmp;
203*a430fa06SMiquel Raynal *ecc_code++ = tmp >> 8;
204*a430fa06SMiquel Raynal *ecc_code++ = tmp >> 16;
205*a430fa06SMiquel Raynal
206*a430fa06SMiquel Raynal /* NOTE: the above code matches mainline Linux:
207*a430fa06SMiquel Raynal * .PQR.stu ==> ~PQRstu
208*a430fa06SMiquel Raynal *
209*a430fa06SMiquel Raynal * MontaVista/TI kernels encode those bytes differently, use
210*a430fa06SMiquel Raynal * complicated (and allegedly sometimes-wrong) correction code,
211*a430fa06SMiquel Raynal * and usually shipped with U-Boot that uses software ECC:
212*a430fa06SMiquel Raynal * .PQR.stu ==> PsQRtu
213*a430fa06SMiquel Raynal *
214*a430fa06SMiquel Raynal * If you need MV/TI compatible NAND I/O in U-Boot, it should
215*a430fa06SMiquel Raynal * be possible to (a) change the mangling above, (b) reverse
216*a430fa06SMiquel Raynal * that mangling in nand_davinci_correct_data() below.
217*a430fa06SMiquel Raynal */
218*a430fa06SMiquel Raynal
219*a430fa06SMiquel Raynal return 0;
220*a430fa06SMiquel Raynal }
221*a430fa06SMiquel Raynal
nand_davinci_correct_data(struct mtd_info * mtd,u_char * dat,u_char * read_ecc,u_char * calc_ecc)222*a430fa06SMiquel Raynal static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
223*a430fa06SMiquel Raynal u_char *read_ecc, u_char *calc_ecc)
224*a430fa06SMiquel Raynal {
225*a430fa06SMiquel Raynal struct nand_chip *this = mtd_to_nand(mtd);
226*a430fa06SMiquel Raynal u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
227*a430fa06SMiquel Raynal (read_ecc[2] << 16);
228*a430fa06SMiquel Raynal u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
229*a430fa06SMiquel Raynal (calc_ecc[2] << 16);
230*a430fa06SMiquel Raynal u_int32_t diff = ecc_calc ^ ecc_nand;
231*a430fa06SMiquel Raynal
232*a430fa06SMiquel Raynal if (diff) {
233*a430fa06SMiquel Raynal if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
234*a430fa06SMiquel Raynal /* Correctable error */
235*a430fa06SMiquel Raynal if ((diff >> (12 + 3)) < this->ecc.size) {
236*a430fa06SMiquel Raynal uint8_t find_bit = 1 << ((diff >> 12) & 7);
237*a430fa06SMiquel Raynal uint32_t find_byte = diff >> (12 + 3);
238*a430fa06SMiquel Raynal
239*a430fa06SMiquel Raynal dat[find_byte] ^= find_bit;
240*a430fa06SMiquel Raynal pr_debug("Correcting single "
241*a430fa06SMiquel Raynal "bit ECC error at offset: %d, bit: "
242*a430fa06SMiquel Raynal "%d\n", find_byte, find_bit);
243*a430fa06SMiquel Raynal return 1;
244*a430fa06SMiquel Raynal } else {
245*a430fa06SMiquel Raynal return -EBADMSG;
246*a430fa06SMiquel Raynal }
247*a430fa06SMiquel Raynal } else if (!(diff & (diff - 1))) {
248*a430fa06SMiquel Raynal /* Single bit ECC error in the ECC itself,
249*a430fa06SMiquel Raynal nothing to fix */
250*a430fa06SMiquel Raynal pr_debug("Single bit ECC error in " "ECC.\n");
251*a430fa06SMiquel Raynal return 1;
252*a430fa06SMiquel Raynal } else {
253*a430fa06SMiquel Raynal /* Uncorrectable error */
254*a430fa06SMiquel Raynal pr_debug("ECC UNCORRECTED_ERROR 1\n");
255*a430fa06SMiquel Raynal return -EBADMSG;
256*a430fa06SMiquel Raynal }
257*a430fa06SMiquel Raynal }
258*a430fa06SMiquel Raynal return 0;
259*a430fa06SMiquel Raynal }
260*a430fa06SMiquel Raynal #endif /* CONFIG_SYS_NAND_HW_ECC */
261*a430fa06SMiquel Raynal
262*a430fa06SMiquel Raynal #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
263*a430fa06SMiquel Raynal static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
264*a430fa06SMiquel Raynal #if defined(CONFIG_SYS_NAND_PAGE_2K)
265*a430fa06SMiquel Raynal .eccbytes = 40,
266*a430fa06SMiquel Raynal #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
267*a430fa06SMiquel Raynal .eccpos = {
268*a430fa06SMiquel Raynal 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
269*a430fa06SMiquel Raynal 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
270*a430fa06SMiquel Raynal 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
271*a430fa06SMiquel Raynal 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
272*a430fa06SMiquel Raynal },
273*a430fa06SMiquel Raynal .oobfree = {
274*a430fa06SMiquel Raynal {2, 4}, {16, 6}, {32, 6}, {48, 6},
275*a430fa06SMiquel Raynal },
276*a430fa06SMiquel Raynal #else
277*a430fa06SMiquel Raynal .eccpos = {
278*a430fa06SMiquel Raynal 24, 25, 26, 27, 28,
279*a430fa06SMiquel Raynal 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
280*a430fa06SMiquel Raynal 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
281*a430fa06SMiquel Raynal 49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
282*a430fa06SMiquel Raynal 59, 60, 61, 62, 63,
283*a430fa06SMiquel Raynal },
284*a430fa06SMiquel Raynal .oobfree = {
285*a430fa06SMiquel Raynal {.offset = 2, .length = 22, },
286*a430fa06SMiquel Raynal },
287*a430fa06SMiquel Raynal #endif /* #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC */
288*a430fa06SMiquel Raynal #elif defined(CONFIG_SYS_NAND_PAGE_4K)
289*a430fa06SMiquel Raynal .eccbytes = 80,
290*a430fa06SMiquel Raynal .eccpos = {
291*a430fa06SMiquel Raynal 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
292*a430fa06SMiquel Raynal 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
293*a430fa06SMiquel Raynal 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
294*a430fa06SMiquel Raynal 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
295*a430fa06SMiquel Raynal 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
296*a430fa06SMiquel Raynal 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
297*a430fa06SMiquel Raynal 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
298*a430fa06SMiquel Raynal 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
299*a430fa06SMiquel Raynal },
300*a430fa06SMiquel Raynal .oobfree = {
301*a430fa06SMiquel Raynal {.offset = 2, .length = 46, },
302*a430fa06SMiquel Raynal },
303*a430fa06SMiquel Raynal #endif
304*a430fa06SMiquel Raynal };
305*a430fa06SMiquel Raynal
306*a430fa06SMiquel Raynal #if defined CONFIG_KEYSTONE_RBL_NAND
307*a430fa06SMiquel Raynal static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = {
308*a430fa06SMiquel Raynal #if defined(CONFIG_SYS_NAND_PAGE_2K)
309*a430fa06SMiquel Raynal .eccbytes = 40,
310*a430fa06SMiquel Raynal .eccpos = {
311*a430fa06SMiquel Raynal 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
312*a430fa06SMiquel Raynal 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
313*a430fa06SMiquel Raynal 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
314*a430fa06SMiquel Raynal 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
315*a430fa06SMiquel Raynal },
316*a430fa06SMiquel Raynal .oobfree = {
317*a430fa06SMiquel Raynal {.offset = 2, .length = 4, },
318*a430fa06SMiquel Raynal {.offset = 16, .length = 6, },
319*a430fa06SMiquel Raynal {.offset = 32, .length = 6, },
320*a430fa06SMiquel Raynal {.offset = 48, .length = 6, },
321*a430fa06SMiquel Raynal },
322*a430fa06SMiquel Raynal #elif defined(CONFIG_SYS_NAND_PAGE_4K)
323*a430fa06SMiquel Raynal .eccbytes = 80,
324*a430fa06SMiquel Raynal .eccpos = {
325*a430fa06SMiquel Raynal 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
326*a430fa06SMiquel Raynal 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
327*a430fa06SMiquel Raynal 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
328*a430fa06SMiquel Raynal 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
329*a430fa06SMiquel Raynal 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
330*a430fa06SMiquel Raynal 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
331*a430fa06SMiquel Raynal 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,
332*a430fa06SMiquel Raynal 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
333*a430fa06SMiquel Raynal },
334*a430fa06SMiquel Raynal .oobfree = {
335*a430fa06SMiquel Raynal {.offset = 2, .length = 4, },
336*a430fa06SMiquel Raynal {.offset = 16, .length = 6, },
337*a430fa06SMiquel Raynal {.offset = 32, .length = 6, },
338*a430fa06SMiquel Raynal {.offset = 48, .length = 6, },
339*a430fa06SMiquel Raynal {.offset = 64, .length = 6, },
340*a430fa06SMiquel Raynal {.offset = 80, .length = 6, },
341*a430fa06SMiquel Raynal {.offset = 96, .length = 6, },
342*a430fa06SMiquel Raynal {.offset = 112, .length = 6, },
343*a430fa06SMiquel Raynal },
344*a430fa06SMiquel Raynal #endif
345*a430fa06SMiquel Raynal };
346*a430fa06SMiquel Raynal
347*a430fa06SMiquel Raynal #ifdef CONFIG_SYS_NAND_PAGE_2K
348*a430fa06SMiquel Raynal #define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 11
349*a430fa06SMiquel Raynal #elif defined(CONFIG_SYS_NAND_PAGE_4K)
350*a430fa06SMiquel Raynal #define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 12
351*a430fa06SMiquel Raynal #endif
352*a430fa06SMiquel Raynal
353*a430fa06SMiquel Raynal /**
354*a430fa06SMiquel Raynal * nand_davinci_write_page - write one page
355*a430fa06SMiquel Raynal * @mtd: MTD device structure
356*a430fa06SMiquel Raynal * @chip: NAND chip descriptor
357*a430fa06SMiquel Raynal * @buf: the data to write
358*a430fa06SMiquel Raynal * @oob_required: must write chip->oob_poi to OOB
359*a430fa06SMiquel Raynal * @page: page number to write
360*a430fa06SMiquel Raynal * @raw: use _raw version of write_page
361*a430fa06SMiquel Raynal */
nand_davinci_write_page(struct mtd_info * mtd,struct nand_chip * chip,uint32_t offset,int data_len,const uint8_t * buf,int oob_required,int page,int raw)362*a430fa06SMiquel Raynal static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip,
363*a430fa06SMiquel Raynal uint32_t offset, int data_len,
364*a430fa06SMiquel Raynal const uint8_t *buf, int oob_required,
365*a430fa06SMiquel Raynal int page, int raw)
366*a430fa06SMiquel Raynal {
367*a430fa06SMiquel Raynal int status;
368*a430fa06SMiquel Raynal int ret = 0;
369*a430fa06SMiquel Raynal struct nand_ecclayout *saved_ecc_layout;
370*a430fa06SMiquel Raynal
371*a430fa06SMiquel Raynal /* save current ECC layout and assign Keystone RBL ECC layout */
372*a430fa06SMiquel Raynal if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
373*a430fa06SMiquel Raynal saved_ecc_layout = chip->ecc.layout;
374*a430fa06SMiquel Raynal chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
375*a430fa06SMiquel Raynal mtd->oobavail = chip->ecc.layout->oobavail;
376*a430fa06SMiquel Raynal }
377*a430fa06SMiquel Raynal
378*a430fa06SMiquel Raynal chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
379*a430fa06SMiquel Raynal
380*a430fa06SMiquel Raynal if (unlikely(raw)) {
381*a430fa06SMiquel Raynal status = chip->ecc.write_page_raw(mtd, chip, buf,
382*a430fa06SMiquel Raynal oob_required, page);
383*a430fa06SMiquel Raynal } else {
384*a430fa06SMiquel Raynal status = chip->ecc.write_page(mtd, chip, buf,
385*a430fa06SMiquel Raynal oob_required, page);
386*a430fa06SMiquel Raynal }
387*a430fa06SMiquel Raynal
388*a430fa06SMiquel Raynal if (status < 0) {
389*a430fa06SMiquel Raynal ret = status;
390*a430fa06SMiquel Raynal goto err;
391*a430fa06SMiquel Raynal }
392*a430fa06SMiquel Raynal
393*a430fa06SMiquel Raynal chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
394*a430fa06SMiquel Raynal status = chip->waitfunc(mtd, chip);
395*a430fa06SMiquel Raynal
396*a430fa06SMiquel Raynal if (status & NAND_STATUS_FAIL) {
397*a430fa06SMiquel Raynal ret = -EIO;
398*a430fa06SMiquel Raynal goto err;
399*a430fa06SMiquel Raynal }
400*a430fa06SMiquel Raynal
401*a430fa06SMiquel Raynal err:
402*a430fa06SMiquel Raynal /* restore ECC layout */
403*a430fa06SMiquel Raynal if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
404*a430fa06SMiquel Raynal chip->ecc.layout = saved_ecc_layout;
405*a430fa06SMiquel Raynal mtd->oobavail = saved_ecc_layout->oobavail;
406*a430fa06SMiquel Raynal }
407*a430fa06SMiquel Raynal
408*a430fa06SMiquel Raynal return ret;
409*a430fa06SMiquel Raynal }
410*a430fa06SMiquel Raynal
411*a430fa06SMiquel Raynal /**
412*a430fa06SMiquel Raynal * nand_davinci_read_page_hwecc - hardware ECC based page read function
413*a430fa06SMiquel Raynal * @mtd: mtd info structure
414*a430fa06SMiquel Raynal * @chip: nand chip info structure
415*a430fa06SMiquel Raynal * @buf: buffer to store read data
416*a430fa06SMiquel Raynal * @oob_required: caller requires OOB data read to chip->oob_poi
417*a430fa06SMiquel Raynal * @page: page number to read
418*a430fa06SMiquel Raynal *
419*a430fa06SMiquel Raynal * Not for syndrome calculating ECC controllers which need a special oob layout.
420*a430fa06SMiquel Raynal */
nand_davinci_read_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)421*a430fa06SMiquel Raynal static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
422*a430fa06SMiquel Raynal uint8_t *buf, int oob_required, int page)
423*a430fa06SMiquel Raynal {
424*a430fa06SMiquel Raynal int i, eccsize = chip->ecc.size;
425*a430fa06SMiquel Raynal int eccbytes = chip->ecc.bytes;
426*a430fa06SMiquel Raynal int eccsteps = chip->ecc.steps;
427*a430fa06SMiquel Raynal uint32_t *eccpos;
428*a430fa06SMiquel Raynal uint8_t *p = buf;
429*a430fa06SMiquel Raynal uint8_t *ecc_code = chip->buffers->ecccode;
430*a430fa06SMiquel Raynal uint8_t *ecc_calc = chip->buffers->ecccalc;
431*a430fa06SMiquel Raynal struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout;
432*a430fa06SMiquel Raynal
433*a430fa06SMiquel Raynal /* save current ECC layout and assign Keystone RBL ECC layout */
434*a430fa06SMiquel Raynal if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
435*a430fa06SMiquel Raynal chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
436*a430fa06SMiquel Raynal mtd->oobavail = chip->ecc.layout->oobavail;
437*a430fa06SMiquel Raynal }
438*a430fa06SMiquel Raynal
439*a430fa06SMiquel Raynal eccpos = chip->ecc.layout->eccpos;
440*a430fa06SMiquel Raynal
441*a430fa06SMiquel Raynal /* Read the OOB area first */
442*a430fa06SMiquel Raynal chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
443*a430fa06SMiquel Raynal chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
444*a430fa06SMiquel Raynal chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
445*a430fa06SMiquel Raynal
446*a430fa06SMiquel Raynal for (i = 0; i < chip->ecc.total; i++)
447*a430fa06SMiquel Raynal ecc_code[i] = chip->oob_poi[eccpos[i]];
448*a430fa06SMiquel Raynal
449*a430fa06SMiquel Raynal for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
450*a430fa06SMiquel Raynal int stat;
451*a430fa06SMiquel Raynal
452*a430fa06SMiquel Raynal chip->ecc.hwctl(mtd, NAND_ECC_READ);
453*a430fa06SMiquel Raynal chip->read_buf(mtd, p, eccsize);
454*a430fa06SMiquel Raynal chip->ecc.calculate(mtd, p, &ecc_calc[i]);
455*a430fa06SMiquel Raynal
456*a430fa06SMiquel Raynal stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
457*a430fa06SMiquel Raynal if (stat < 0)
458*a430fa06SMiquel Raynal mtd->ecc_stats.failed++;
459*a430fa06SMiquel Raynal else
460*a430fa06SMiquel Raynal mtd->ecc_stats.corrected += stat;
461*a430fa06SMiquel Raynal }
462*a430fa06SMiquel Raynal
463*a430fa06SMiquel Raynal /* restore ECC layout */
464*a430fa06SMiquel Raynal if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
465*a430fa06SMiquel Raynal chip->ecc.layout = saved_ecc_layout;
466*a430fa06SMiquel Raynal mtd->oobavail = saved_ecc_layout->oobavail;
467*a430fa06SMiquel Raynal }
468*a430fa06SMiquel Raynal
469*a430fa06SMiquel Raynal return 0;
470*a430fa06SMiquel Raynal }
471*a430fa06SMiquel Raynal #endif /* CONFIG_KEYSTONE_RBL_NAND */
472*a430fa06SMiquel Raynal
nand_davinci_4bit_enable_hwecc(struct mtd_info * mtd,int mode)473*a430fa06SMiquel Raynal static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
474*a430fa06SMiquel Raynal {
475*a430fa06SMiquel Raynal u32 val;
476*a430fa06SMiquel Raynal
477*a430fa06SMiquel Raynal switch (mode) {
478*a430fa06SMiquel Raynal case NAND_ECC_WRITE:
479*a430fa06SMiquel Raynal case NAND_ECC_READ:
480*a430fa06SMiquel Raynal /*
481*a430fa06SMiquel Raynal * Start a new ECC calculation for reading or writing 512 bytes
482*a430fa06SMiquel Raynal * of data.
483*a430fa06SMiquel Raynal */
484*a430fa06SMiquel Raynal val = __raw_readl(&davinci_emif_regs->nandfcr);
485*a430fa06SMiquel Raynal val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
486*a430fa06SMiquel Raynal val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
487*a430fa06SMiquel Raynal val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
488*a430fa06SMiquel Raynal val |= DAVINCI_NANDFCR_4BIT_ECC_START;
489*a430fa06SMiquel Raynal __raw_writel(val, &davinci_emif_regs->nandfcr);
490*a430fa06SMiquel Raynal break;
491*a430fa06SMiquel Raynal case NAND_ECC_READSYN:
492*a430fa06SMiquel Raynal val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]);
493*a430fa06SMiquel Raynal break;
494*a430fa06SMiquel Raynal default:
495*a430fa06SMiquel Raynal break;
496*a430fa06SMiquel Raynal }
497*a430fa06SMiquel Raynal }
498*a430fa06SMiquel Raynal
nand_davinci_4bit_readecc(struct mtd_info * mtd,unsigned int ecc[4])499*a430fa06SMiquel Raynal static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
500*a430fa06SMiquel Raynal {
501*a430fa06SMiquel Raynal int i;
502*a430fa06SMiquel Raynal
503*a430fa06SMiquel Raynal for (i = 0; i < 4; i++) {
504*a430fa06SMiquel Raynal ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) &
505*a430fa06SMiquel Raynal NAND_4BITECC_MASK;
506*a430fa06SMiquel Raynal }
507*a430fa06SMiquel Raynal
508*a430fa06SMiquel Raynal return 0;
509*a430fa06SMiquel Raynal }
510*a430fa06SMiquel Raynal
nand_davinci_4bit_calculate_ecc(struct mtd_info * mtd,const uint8_t * dat,uint8_t * ecc_code)511*a430fa06SMiquel Raynal static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
512*a430fa06SMiquel Raynal const uint8_t *dat,
513*a430fa06SMiquel Raynal uint8_t *ecc_code)
514*a430fa06SMiquel Raynal {
515*a430fa06SMiquel Raynal unsigned int hw_4ecc[4];
516*a430fa06SMiquel Raynal unsigned int i;
517*a430fa06SMiquel Raynal
518*a430fa06SMiquel Raynal nand_davinci_4bit_readecc(mtd, hw_4ecc);
519*a430fa06SMiquel Raynal
520*a430fa06SMiquel Raynal /*Convert 10 bit ecc value to 8 bit */
521*a430fa06SMiquel Raynal for (i = 0; i < 2; i++) {
522*a430fa06SMiquel Raynal unsigned int hw_ecc_low = hw_4ecc[i * 2];
523*a430fa06SMiquel Raynal unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1];
524*a430fa06SMiquel Raynal
525*a430fa06SMiquel Raynal /* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
526*a430fa06SMiquel Raynal *ecc_code++ = hw_ecc_low & 0xFF;
527*a430fa06SMiquel Raynal
528*a430fa06SMiquel Raynal /*
529*a430fa06SMiquel Raynal * Take 2 bits as LSB bits from val1 (count1=0) or val5
530*a430fa06SMiquel Raynal * (count1=1) and 6 bits from val2 (count1=0) or
531*a430fa06SMiquel Raynal * val5 (count1=1)
532*a430fa06SMiquel Raynal */
533*a430fa06SMiquel Raynal *ecc_code++ =
534*a430fa06SMiquel Raynal ((hw_ecc_low >> 8) & 0x3) | ((hw_ecc_low >> 14) & 0xFC);
535*a430fa06SMiquel Raynal
536*a430fa06SMiquel Raynal /*
537*a430fa06SMiquel Raynal * Take 4 bits from val2 (count1=0) or val5 (count1=1) and
538*a430fa06SMiquel Raynal * 4 bits from val3 (count1=0) or val6 (count1=1)
539*a430fa06SMiquel Raynal */
540*a430fa06SMiquel Raynal *ecc_code++ =
541*a430fa06SMiquel Raynal ((hw_ecc_low >> 22) & 0xF) | ((hw_ecc_hi << 4) & 0xF0);
542*a430fa06SMiquel Raynal
543*a430fa06SMiquel Raynal /*
544*a430fa06SMiquel Raynal * Take 6 bits from val3(count1=0) or val6 (count1=1) and
545*a430fa06SMiquel Raynal * 2 bits from val4 (count1=0) or val7 (count1=1)
546*a430fa06SMiquel Raynal */
547*a430fa06SMiquel Raynal *ecc_code++ =
548*a430fa06SMiquel Raynal ((hw_ecc_hi >> 4) & 0x3F) | ((hw_ecc_hi >> 10) & 0xC0);
549*a430fa06SMiquel Raynal
550*a430fa06SMiquel Raynal /* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
551*a430fa06SMiquel Raynal *ecc_code++ = (hw_ecc_hi >> 18) & 0xFF;
552*a430fa06SMiquel Raynal }
553*a430fa06SMiquel Raynal
554*a430fa06SMiquel Raynal return 0;
555*a430fa06SMiquel Raynal }
556*a430fa06SMiquel Raynal
nand_davinci_4bit_correct_data(struct mtd_info * mtd,uint8_t * dat,uint8_t * read_ecc,uint8_t * calc_ecc)557*a430fa06SMiquel Raynal static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
558*a430fa06SMiquel Raynal uint8_t *read_ecc, uint8_t *calc_ecc)
559*a430fa06SMiquel Raynal {
560*a430fa06SMiquel Raynal int i;
561*a430fa06SMiquel Raynal unsigned int hw_4ecc[4];
562*a430fa06SMiquel Raynal unsigned int iserror;
563*a430fa06SMiquel Raynal unsigned short *ecc16;
564*a430fa06SMiquel Raynal unsigned int numerrors, erroraddress, errorvalue;
565*a430fa06SMiquel Raynal u32 val;
566*a430fa06SMiquel Raynal
567*a430fa06SMiquel Raynal /*
568*a430fa06SMiquel Raynal * Check for an ECC where all bytes are 0xFF. If this is the case, we
569*a430fa06SMiquel Raynal * will assume we are looking at an erased page and we should ignore
570*a430fa06SMiquel Raynal * the ECC.
571*a430fa06SMiquel Raynal */
572*a430fa06SMiquel Raynal for (i = 0; i < 10; i++) {
573*a430fa06SMiquel Raynal if (read_ecc[i] != 0xFF)
574*a430fa06SMiquel Raynal break;
575*a430fa06SMiquel Raynal }
576*a430fa06SMiquel Raynal if (i == 10)
577*a430fa06SMiquel Raynal return 0;
578*a430fa06SMiquel Raynal
579*a430fa06SMiquel Raynal /* Convert 8 bit in to 10 bit */
580*a430fa06SMiquel Raynal ecc16 = (unsigned short *)&read_ecc[0];
581*a430fa06SMiquel Raynal
582*a430fa06SMiquel Raynal /*
583*a430fa06SMiquel Raynal * Write the parity values in the NAND Flash 4-bit ECC Load register.
584*a430fa06SMiquel Raynal * Write each parity value one at a time starting from 4bit_ecc_val8
585*a430fa06SMiquel Raynal * to 4bit_ecc_val1.
586*a430fa06SMiquel Raynal */
587*a430fa06SMiquel Raynal
588*a430fa06SMiquel Raynal /*Take 2 bits from 8th byte and 8 bits from 9th byte */
589*a430fa06SMiquel Raynal __raw_writel(((ecc16[4]) >> 6) & 0x3FF,
590*a430fa06SMiquel Raynal &davinci_emif_regs->nand4biteccload);
591*a430fa06SMiquel Raynal
592*a430fa06SMiquel Raynal /* Take 4 bits from 7th byte and 6 bits from 8th byte */
593*a430fa06SMiquel Raynal __raw_writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
594*a430fa06SMiquel Raynal &davinci_emif_regs->nand4biteccload);
595*a430fa06SMiquel Raynal
596*a430fa06SMiquel Raynal /* Take 6 bits from 6th byte and 4 bits from 7th byte */
597*a430fa06SMiquel Raynal __raw_writel((ecc16[3] >> 2) & 0x3FF,
598*a430fa06SMiquel Raynal &davinci_emif_regs->nand4biteccload);
599*a430fa06SMiquel Raynal
600*a430fa06SMiquel Raynal /* Take 8 bits from 5th byte and 2 bits from 6th byte */
601*a430fa06SMiquel Raynal __raw_writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
602*a430fa06SMiquel Raynal &davinci_emif_regs->nand4biteccload);
603*a430fa06SMiquel Raynal
604*a430fa06SMiquel Raynal /*Take 2 bits from 3rd byte and 8 bits from 4th byte */
605*a430fa06SMiquel Raynal __raw_writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
606*a430fa06SMiquel Raynal &davinci_emif_regs->nand4biteccload);
607*a430fa06SMiquel Raynal
608*a430fa06SMiquel Raynal /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
609*a430fa06SMiquel Raynal __raw_writel(((ecc16[1]) >> 4) & 0x3FF,
610*a430fa06SMiquel Raynal &davinci_emif_regs->nand4biteccload);
611*a430fa06SMiquel Raynal
612*a430fa06SMiquel Raynal /* Take 6 bits from 1st byte and 4 bits from 2nd byte */
613*a430fa06SMiquel Raynal __raw_writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
614*a430fa06SMiquel Raynal &davinci_emif_regs->nand4biteccload);
615*a430fa06SMiquel Raynal
616*a430fa06SMiquel Raynal /* Take 10 bits from 0th and 1st bytes */
617*a430fa06SMiquel Raynal __raw_writel((ecc16[0]) & 0x3FF,
618*a430fa06SMiquel Raynal &davinci_emif_regs->nand4biteccload);
619*a430fa06SMiquel Raynal
620*a430fa06SMiquel Raynal /*
621*a430fa06SMiquel Raynal * Perform a dummy read to the EMIF Revision Code and Status register.
622*a430fa06SMiquel Raynal * This is required to ensure time for syndrome calculation after
623*a430fa06SMiquel Raynal * writing the ECC values in previous step.
624*a430fa06SMiquel Raynal */
625*a430fa06SMiquel Raynal
626*a430fa06SMiquel Raynal val = __raw_readl(&davinci_emif_regs->nandfsr);
627*a430fa06SMiquel Raynal
628*a430fa06SMiquel Raynal /*
629*a430fa06SMiquel Raynal * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
630*a430fa06SMiquel Raynal * A syndrome value of 0 means no bit errors. If the syndrome is
631*a430fa06SMiquel Raynal * non-zero then go further otherwise return.
632*a430fa06SMiquel Raynal */
633*a430fa06SMiquel Raynal nand_davinci_4bit_readecc(mtd, hw_4ecc);
634*a430fa06SMiquel Raynal
635*a430fa06SMiquel Raynal if (!(hw_4ecc[0] | hw_4ecc[1] | hw_4ecc[2] | hw_4ecc[3]))
636*a430fa06SMiquel Raynal return 0;
637*a430fa06SMiquel Raynal
638*a430fa06SMiquel Raynal /*
639*a430fa06SMiquel Raynal * Clear any previous address calculation by doing a dummy read of an
640*a430fa06SMiquel Raynal * error address register.
641*a430fa06SMiquel Raynal */
642*a430fa06SMiquel Raynal val = __raw_readl(&davinci_emif_regs->nanderradd1);
643*a430fa06SMiquel Raynal
644*a430fa06SMiquel Raynal /*
645*a430fa06SMiquel Raynal * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
646*a430fa06SMiquel Raynal * register to 1.
647*a430fa06SMiquel Raynal */
648*a430fa06SMiquel Raynal __raw_writel(DAVINCI_NANDFCR_4BIT_CALC_START,
649*a430fa06SMiquel Raynal &davinci_emif_regs->nandfcr);
650*a430fa06SMiquel Raynal
651*a430fa06SMiquel Raynal /*
652*a430fa06SMiquel Raynal * Wait for the corr_state field (bits 8 to 11) in the
653*a430fa06SMiquel Raynal * NAND Flash Status register to be not equal to 0x0, 0x1, 0x2, or 0x3.
654*a430fa06SMiquel Raynal * Otherwise ECC calculation has not even begun and the next loop might
655*a430fa06SMiquel Raynal * fail because of a false positive!
656*a430fa06SMiquel Raynal */
657*a430fa06SMiquel Raynal i = NAND_TIMEOUT;
658*a430fa06SMiquel Raynal do {
659*a430fa06SMiquel Raynal val = __raw_readl(&davinci_emif_regs->nandfsr);
660*a430fa06SMiquel Raynal val &= 0xc00;
661*a430fa06SMiquel Raynal i--;
662*a430fa06SMiquel Raynal } while ((i > 0) && !val);
663*a430fa06SMiquel Raynal
664*a430fa06SMiquel Raynal /*
665*a430fa06SMiquel Raynal * Wait for the corr_state field (bits 8 to 11) in the
666*a430fa06SMiquel Raynal * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
667*a430fa06SMiquel Raynal */
668*a430fa06SMiquel Raynal i = NAND_TIMEOUT;
669*a430fa06SMiquel Raynal do {
670*a430fa06SMiquel Raynal val = __raw_readl(&davinci_emif_regs->nandfsr);
671*a430fa06SMiquel Raynal val &= 0xc00;
672*a430fa06SMiquel Raynal i--;
673*a430fa06SMiquel Raynal } while ((i > 0) && val);
674*a430fa06SMiquel Raynal
675*a430fa06SMiquel Raynal iserror = __raw_readl(&davinci_emif_regs->nandfsr);
676*a430fa06SMiquel Raynal iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
677*a430fa06SMiquel Raynal iserror = iserror >> 8;
678*a430fa06SMiquel Raynal
679*a430fa06SMiquel Raynal /*
680*a430fa06SMiquel Raynal * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
681*a430fa06SMiquel Raynal * corrected (five or more errors). The number of errors
682*a430fa06SMiquel Raynal * calculated (err_num field) differs from the number of errors
683*a430fa06SMiquel Raynal * searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error
684*a430fa06SMiquel Raynal * correction complete (errors on bit 8 or 9).
685*a430fa06SMiquel Raynal * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
686*a430fa06SMiquel Raynal * complete (error exists).
687*a430fa06SMiquel Raynal */
688*a430fa06SMiquel Raynal
689*a430fa06SMiquel Raynal if (iserror == ECC_STATE_NO_ERR) {
690*a430fa06SMiquel Raynal val = __raw_readl(&davinci_emif_regs->nanderrval1);
691*a430fa06SMiquel Raynal return 0;
692*a430fa06SMiquel Raynal } else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
693*a430fa06SMiquel Raynal val = __raw_readl(&davinci_emif_regs->nanderrval1);
694*a430fa06SMiquel Raynal return -EBADMSG;
695*a430fa06SMiquel Raynal }
696*a430fa06SMiquel Raynal
697*a430fa06SMiquel Raynal numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
698*a430fa06SMiquel Raynal & 0x3) + 1;
699*a430fa06SMiquel Raynal
700*a430fa06SMiquel Raynal /* Read the error address, error value and correct */
701*a430fa06SMiquel Raynal for (i = 0; i < numerrors; i++) {
702*a430fa06SMiquel Raynal if (i > 1) {
703*a430fa06SMiquel Raynal erroraddress =
704*a430fa06SMiquel Raynal ((__raw_readl(&davinci_emif_regs->nanderradd2) >>
705*a430fa06SMiquel Raynal (16 * (i & 1))) & 0x3FF);
706*a430fa06SMiquel Raynal erroraddress = ((512 + 7) - erroraddress);
707*a430fa06SMiquel Raynal errorvalue =
708*a430fa06SMiquel Raynal ((__raw_readl(&davinci_emif_regs->nanderrval2) >>
709*a430fa06SMiquel Raynal (16 * (i & 1))) & 0xFF);
710*a430fa06SMiquel Raynal } else {
711*a430fa06SMiquel Raynal erroraddress =
712*a430fa06SMiquel Raynal ((__raw_readl(&davinci_emif_regs->nanderradd1) >>
713*a430fa06SMiquel Raynal (16 * (i & 1))) & 0x3FF);
714*a430fa06SMiquel Raynal erroraddress = ((512 + 7) - erroraddress);
715*a430fa06SMiquel Raynal errorvalue =
716*a430fa06SMiquel Raynal ((__raw_readl(&davinci_emif_regs->nanderrval1) >>
717*a430fa06SMiquel Raynal (16 * (i & 1))) & 0xFF);
718*a430fa06SMiquel Raynal }
719*a430fa06SMiquel Raynal /* xor the corrupt data with error value */
720*a430fa06SMiquel Raynal if (erroraddress < 512)
721*a430fa06SMiquel Raynal dat[erroraddress] ^= errorvalue;
722*a430fa06SMiquel Raynal }
723*a430fa06SMiquel Raynal
724*a430fa06SMiquel Raynal return numerrors;
725*a430fa06SMiquel Raynal }
726*a430fa06SMiquel Raynal #endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */
727*a430fa06SMiquel Raynal
nand_davinci_dev_ready(struct mtd_info * mtd)728*a430fa06SMiquel Raynal static int nand_davinci_dev_ready(struct mtd_info *mtd)
729*a430fa06SMiquel Raynal {
730*a430fa06SMiquel Raynal return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
731*a430fa06SMiquel Raynal }
732*a430fa06SMiquel Raynal
nand_flash_init(void)733*a430fa06SMiquel Raynal static void nand_flash_init(void)
734*a430fa06SMiquel Raynal {
735*a430fa06SMiquel Raynal /* This is for DM6446 EVM and *very* similar. DO NOT GROW THIS!
736*a430fa06SMiquel Raynal * Instead, have your board_init() set EMIF timings, based on its
737*a430fa06SMiquel Raynal * knowledge of the clocks and what devices are hooked up ... and
738*a430fa06SMiquel Raynal * don't even do that unless no UBL handled it.
739*a430fa06SMiquel Raynal */
740*a430fa06SMiquel Raynal #ifdef CONFIG_SOC_DM644X
741*a430fa06SMiquel Raynal u_int32_t acfg1 = 0x3ffffffc;
742*a430fa06SMiquel Raynal
743*a430fa06SMiquel Raynal /*------------------------------------------------------------------*
744*a430fa06SMiquel Raynal * NAND FLASH CHIP TIMEOUT @ 459 MHz *
745*a430fa06SMiquel Raynal * *
746*a430fa06SMiquel Raynal * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
747*a430fa06SMiquel Raynal * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
748*a430fa06SMiquel Raynal * *
749*a430fa06SMiquel Raynal *------------------------------------------------------------------*/
750*a430fa06SMiquel Raynal acfg1 = 0
751*a430fa06SMiquel Raynal | (0 << 31) /* selectStrobe */
752*a430fa06SMiquel Raynal | (0 << 30) /* extWait */
753*a430fa06SMiquel Raynal | (1 << 26) /* writeSetup 10 ns */
754*a430fa06SMiquel Raynal | (3 << 20) /* writeStrobe 40 ns */
755*a430fa06SMiquel Raynal | (1 << 17) /* writeHold 10 ns */
756*a430fa06SMiquel Raynal | (1 << 13) /* readSetup 10 ns */
757*a430fa06SMiquel Raynal | (5 << 7) /* readStrobe 60 ns */
758*a430fa06SMiquel Raynal | (1 << 4) /* readHold 10 ns */
759*a430fa06SMiquel Raynal | (3 << 2) /* turnAround ?? ns */
760*a430fa06SMiquel Raynal | (0 << 0) /* asyncSize 8-bit bus */
761*a430fa06SMiquel Raynal ;
762*a430fa06SMiquel Raynal
763*a430fa06SMiquel Raynal __raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */
764*a430fa06SMiquel Raynal
765*a430fa06SMiquel Raynal /* NAND flash on CS2 */
766*a430fa06SMiquel Raynal __raw_writel(0x00000101, &davinci_emif_regs->nandfcr);
767*a430fa06SMiquel Raynal #endif
768*a430fa06SMiquel Raynal }
769*a430fa06SMiquel Raynal
davinci_nand_init(struct nand_chip * nand)770*a430fa06SMiquel Raynal void davinci_nand_init(struct nand_chip *nand)
771*a430fa06SMiquel Raynal {
772*a430fa06SMiquel Raynal #if defined CONFIG_KEYSTONE_RBL_NAND
773*a430fa06SMiquel Raynal int i;
774*a430fa06SMiquel Raynal struct nand_ecclayout *layout;
775*a430fa06SMiquel Raynal
776*a430fa06SMiquel Raynal layout = &nand_keystone_rbl_4bit_layout_oobfirst;
777*a430fa06SMiquel Raynal layout->oobavail = 0;
778*a430fa06SMiquel Raynal for (i = 0; layout->oobfree[i].length &&
779*a430fa06SMiquel Raynal i < ARRAY_SIZE(layout->oobfree); i++)
780*a430fa06SMiquel Raynal layout->oobavail += layout->oobfree[i].length;
781*a430fa06SMiquel Raynal
782*a430fa06SMiquel Raynal nand->write_page = nand_davinci_write_page;
783*a430fa06SMiquel Raynal nand->ecc.read_page = nand_davinci_read_page_hwecc;
784*a430fa06SMiquel Raynal #endif
785*a430fa06SMiquel Raynal nand->chip_delay = 0;
786*a430fa06SMiquel Raynal #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
787*a430fa06SMiquel Raynal nand->bbt_options |= NAND_BBT_USE_FLASH;
788*a430fa06SMiquel Raynal #endif
789*a430fa06SMiquel Raynal #ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
790*a430fa06SMiquel Raynal nand->options |= NAND_NO_SUBPAGE_WRITE;
791*a430fa06SMiquel Raynal #endif
792*a430fa06SMiquel Raynal #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
793*a430fa06SMiquel Raynal nand->options |= NAND_BUSWIDTH_16;
794*a430fa06SMiquel Raynal #endif
795*a430fa06SMiquel Raynal #ifdef CONFIG_SYS_NAND_HW_ECC
796*a430fa06SMiquel Raynal nand->ecc.mode = NAND_ECC_HW;
797*a430fa06SMiquel Raynal nand->ecc.size = 512;
798*a430fa06SMiquel Raynal nand->ecc.bytes = 3;
799*a430fa06SMiquel Raynal nand->ecc.strength = 1;
800*a430fa06SMiquel Raynal nand->ecc.calculate = nand_davinci_calculate_ecc;
801*a430fa06SMiquel Raynal nand->ecc.correct = nand_davinci_correct_data;
802*a430fa06SMiquel Raynal nand->ecc.hwctl = nand_davinci_enable_hwecc;
803*a430fa06SMiquel Raynal #else
804*a430fa06SMiquel Raynal nand->ecc.mode = NAND_ECC_SOFT;
805*a430fa06SMiquel Raynal #endif /* CONFIG_SYS_NAND_HW_ECC */
806*a430fa06SMiquel Raynal #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
807*a430fa06SMiquel Raynal nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
808*a430fa06SMiquel Raynal nand->ecc.size = 512;
809*a430fa06SMiquel Raynal nand->ecc.bytes = 10;
810*a430fa06SMiquel Raynal nand->ecc.strength = 4;
811*a430fa06SMiquel Raynal nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
812*a430fa06SMiquel Raynal nand->ecc.correct = nand_davinci_4bit_correct_data;
813*a430fa06SMiquel Raynal nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
814*a430fa06SMiquel Raynal nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
815*a430fa06SMiquel Raynal #endif
816*a430fa06SMiquel Raynal /* Set address of hardware control function */
817*a430fa06SMiquel Raynal nand->cmd_ctrl = nand_davinci_hwcontrol;
818*a430fa06SMiquel Raynal
819*a430fa06SMiquel Raynal nand->read_buf = nand_davinci_read_buf;
820*a430fa06SMiquel Raynal nand->write_buf = nand_davinci_write_buf;
821*a430fa06SMiquel Raynal
822*a430fa06SMiquel Raynal nand->dev_ready = nand_davinci_dev_ready;
823*a430fa06SMiquel Raynal
824*a430fa06SMiquel Raynal nand_flash_init();
825*a430fa06SMiquel Raynal }
826*a430fa06SMiquel Raynal
827*a430fa06SMiquel Raynal int board_nand_init(struct nand_chip *chip) __attribute__((weak));
828*a430fa06SMiquel Raynal
board_nand_init(struct nand_chip * chip)829*a430fa06SMiquel Raynal int board_nand_init(struct nand_chip *chip)
830*a430fa06SMiquel Raynal {
831*a430fa06SMiquel Raynal davinci_nand_init(chip);
832*a430fa06SMiquel Raynal return 0;
833*a430fa06SMiquel Raynal }
834