| /openbmc/linux/drivers/gpu/ipu-v3/ |
| H A D | ipu-cpmem.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
11 #include "ipu-prv.h"
30 #define IPU_CPMEM_WORD(word, ofs, size) ((((word) * 160 + (ofs)) << 8) | (size))
93 ipu_get_cpmem(struct ipuv3_channel *ch) in ipu_get_cpmem() argument
95 struct ipu_cpmem *cpmem = ch->ipu->cpmem_priv; in ipu_get_cpmem()
97 return cpmem->base + ch->num; in ipu_get_cpmem()
100 static void ipu_ch_param_write_field(struct ipuv3_channel *ch, u32 wbs, u32 v) in ipu_ch_param_write_field() argument
102 struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch); in ipu_ch_param_write_field()
103 u32 bit = (wbs >> 8) % 160; in ipu_ch_param_write_field()
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| /openbmc/linux/drivers/gpu/drm/imx/dcss/ |
| H A D | dcss-dpr.c | 1 // SPDX-License-Identifier: GPL-2.0
9 #include "dcss-dev.h"
36 #define PIX_SIZE_POS 8
37 #define PIX_SIZE_MASK GENMASK(9, 8)
118 struct dcss_dpr_ch ch[3]; member
121 static void dcss_dpr_write(struct dcss_dpr_ch *ch, u32 val, u32 ofs) in dcss_dpr_write() argument
123 struct dcss_dpr *dpr = ch->dpr; in dcss_dpr_write()
125 dcss_ctxld_write(dpr->ctxld, dpr->ctx_id, val, ch->base_ofs + ofs); in dcss_dpr_write()
130 struct dcss_dpr_ch *ch; in dcss_dpr_ch_init_all() local
134 ch = &dpr->ch[i]; in dcss_dpr_ch_init_all()
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| H A D | dcss-scaler.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #include "dcss-dev.h"
16 #define SCALE2MEM_EN BIT(8)
33 #define A2R10G10B10_FORMAT_POS 8
34 #define A2R10G10B10_FORMAT_MASK GENMASK(11, 8)
90 struct dcss_scaler_ch ch[3]; member
103 #define PSC_PHASE_MASK (PSC_NUM_PHASES - 1)
105 #define PSC_Q_ROUND_OFFSET (1 << (PSC_Q_FRACTION - 1))
108 * mult_q() - Performs fixed-point multiplication.
124 * div_q() - Performs fixed-point division.
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| /openbmc/linux/drivers/scsi/ |
| H A D | ch.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * (c) 1996-2003 Gerd Knorr <kraxel@bytesex.org>
38 #define CH_TYPES 8
71 static int dt_id[CH_DT_MAX] = { [ 0 ... (CH_DT_MAX-1) ] = -1 };
76 /* tell the driver about vendor-specific slots */
77 static int vendor_firsts[CH_TYPES-4];
78 static int vendor_counts[CH_TYPES-4];
82 static const char * vendor_labels[CH_TYPES-4] = {
87 #define ch_printk(prefix, ch, fmt, a...) \ argument
88 sdev_prefix_printk(prefix, (ch)->device, (ch)->name, fmt, ##a)
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| /openbmc/qemu/hw/timer/ |
| H A D | renesas_tmr.c | 2 * Renesas 8bit timer
9 * SPDX-License-Identifier: GPL-2.0-or-later
28 #include "hw/qdev-properties.h"
43 REG8(TCNT, 8)
56 static const int clkdiv[] = {0, 1, 2, 8, 32, 64, 1024, 8192};
60 return (reg[0] << 8) | reg[1]; in concat_reg()
63 static void update_events(RTMRState *tmr, int ch) in update_events() argument
69 if (tmr->tccr[ch] == 0) { in update_events()
72 if (FIELD_EX8(tmr->tccr[ch], TCCR, CSS) == 0) { in update_events()
77 if (FIELD_EX8(tmr->tccr[0], TCCR, CSS) == CSS_CASCADING) { in update_events()
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| /openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/dvb-t/ |
| H A D | es-Huesca | 1 # DVB-T Huesca (Aragon) [Spain] [es-Huesca]
3 #------------------------------------------------------------------------------
5 [CH 43 HTV-HuescaTelevision]
12 TRANSMISSION_MODE = 8K
17 [CH 44 La Sexta 2]
24 TRANSMISSION_MODE = 8K
29 [CH 45 TVE HD]
36 TRANSMISSION_MODE = 8K
41 [CH 48 NITRO]
48 TRANSMISSION_MODE = 8K
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| /openbmc/linux/drivers/video/fbdev/ |
| H A D | sh_mobile_lcdcfb.c | 16 #include <linux/dma-mapping.h>
35 /* ----------------------------------------------------------------------------
41 #define LDBCR_UPF(n) (1 << ((n) + 8))
65 #define LDBBSIFR_SWPB (1 << 8)
94 #define LDBBSAYR_FG1G_MASK (0xff << 8)
95 #define LDBBSAYR_FG1G_SHIFT 8
103 #define LDBBSACR_FG2G_MASK (0xff << 8)
104 #define LDBBSACR_FG2G_SHIFT 8
112 #define LDBBSAAR_GY_MASK (0xff << 8)
113 #define LDBBSAAR_GY_SHIFT 8
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| /openbmc/linux/arch/arm/boot/dts/aspeed/ |
| H A D | aspeed-bmc-amd-daytonax.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "aspeed-g5.dtsi"
5 #include <dt-bindings/gpio/aspeed-gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
10 compatible = "amd,daytonax-bmc", "aspeed,ast2500";
16 reserved-memory {
17 #address-cells = <1>;
18 #size-cells = <1>;
24 compatible = "shared-dma-pool";
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| /openbmc/linux/include/linux/mfd/ |
| H A D | rz-mtu3.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 /* 8-bit shared register offsets macros */
16 /* 16-bit shared register offset macros */
31 /* 8-bit register offset macros of MTU3 channels except MTU5 */
48 #define RZ_MTU3_TBTM 8 /* Timer buffer operation transfer mode register */
50 /* 8-bit MTU5 register offset macros */
57 #define RZ_MTU3_TCR2V 8 /* Timer control register 2V */
63 /* 16-bit register offset macros of MTU3 channels except MTU5 */
73 #define RZ_MTU3_TADCORA 8 /* cycle set register A */
78 /* 16-bit MTU5 register offset macros */
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| /openbmc/u-boot/arch/x86/cpu/quark/ |
| H A D | smc.c | 1 // SPDX-License-Identifier: Intel
82 tck = t_ck[mrc_params->ddr_speed]; /* Clock in picoseconds */ in prog_ddr_timing_control()
83 tcl = mrc_params->params.cl; /* CAS latency in clocks */ in prog_ddr_timing_control()
86 tras = MCEIL(mrc_params->params.ras, tck); in prog_ddr_timing_control()
88 /* Per JEDEC: tWR=15000ps DDR2/3 from 800-1600 */ in prog_ddr_timing_control()
91 twtr = MCEIL(mrc_params->params.wtr, tck); in prog_ddr_timing_control()
92 trrd = MCEIL(mrc_params->params.rrd, tck); in prog_ddr_timing_control()
94 tfaw = MCEIL(mrc_params->params.faw, tck); in prog_ddr_timing_control()
96 wl = 5 + mrc_params->ddr_speed; in prog_ddr_timing_control()
99 dtr0 |= mrc_params->ddr_speed; in prog_ddr_timing_control()
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| /openbmc/linux/arch/x86/crypto/ |
| H A D | sha512-avx2-asm.S | 2 # Implement fast SHA-512 with AVX2 instructions. (x86_64)
22 # - Redistributions of source code must retain the above
26 # - Redistributions in binary form must reproduce the above
42 # This code is described in an Intel White-Paper:
43 # "Fast SHA-512 Implementations on Intel Architecture Processors"
101 XFER_SIZE = 4*8
102 SRND_SIZE = 1*8
103 INP_SIZE = 1*8
104 INPEND_SIZE = 1*8
105 CTX_SIZE = 1*8
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| /openbmc/linux/arch/mips/lantiq/xway/ |
| H A D | dma.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
36 #define DMA_TX BIT(8) /* TX channel direction */
46 #define DMA_PCTRL_8W_BURST 0x3 /* 8 word burst length */
49 #define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */
61 ltq_dma_enable_irq(struct ltq_dma_channel *ch) in ltq_dma_enable_irq() argument
66 ltq_dma_w32(ch->nr, LTQ_DMA_CS); in ltq_dma_enable_irq()
67 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); in ltq_dma_enable_irq()
73 ltq_dma_disable_irq(struct ltq_dma_channel *ch) in ltq_dma_disable_irq() argument
78 ltq_dma_w32(ch->nr, LTQ_DMA_CS); in ltq_dma_disable_irq()
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| /openbmc/qemu/hw/dma/ |
| H A D | bcm2835_dma.c | 5 * See the COPYING file in the top-level directory.
22 #define BCM2708_DMA_ERR (1 << 8)
34 #define BCM2708_DMA_S_INC (1 << 8)
42 /* the current control block appears in the following registers - read only */
58 BCM2835DMAChan *ch = &s->chan[c]; in bcm2835_dma_update() local
62 if (!(s->enable & (1 << c))) { in bcm2835_dma_update()
66 while ((s->enable & (1 << c)) && (ch->conblk_ad != 0)) { in bcm2835_dma_update()
68 ch->ti = ldl_le_phys(&s->dma_as, ch->conblk_ad); in bcm2835_dma_update()
69 ch->source_ad = ldl_le_phys(&s->dma_as, ch->conblk_ad + 4); in bcm2835_dma_update()
70 ch->dest_ad = ldl_le_phys(&s->dma_as, ch->conblk_ad + 8); in bcm2835_dma_update()
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| /openbmc/linux/drivers/clk/uniphier/ |
| H A D | clk-uniphier-mio.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include "clk-uniphier.h"
12 UNIPHIER_CLK_FACTOR("sd-44m", -1, "sd-133m", 1, 3), \
13 UNIPHIER_CLK_FACTOR("sd-33m", -1, "sd-200m", 1, 6), \
14 UNIPHIER_CLK_FACTOR("sd-50m", -1, "sd-200m", 1, 4), \
15 UNIPHIER_CLK_FACTOR("sd-67m", -1, "sd-200m", 1, 3), \
16 UNIPHIER_CLK_FACTOR("sd-100m", -1, "sd-200m", 1, 2), \
17 UNIPHIER_CLK_FACTOR("sd-40m", -1, "sd-200m", 1, 5), \
18 UNIPHIER_CLK_FACTOR("sd-25m", -1, "sd-200m", 1, 8), \
19 UNIPHIER_CLK_FACTOR("sd-22m", -1, "sd-133m", 1, 6)
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| /openbmc/linux/lib/ |
| H A D | hexdump.c | 1 // SPDX-License-Identifier: GPL-2.0-only
20 * hex_to_bin - convert a hex digit to its real value
21 * @ch: ascii character represents hex digit
23 * hex_to_bin() converts one hex digit to its actual value or -1 in case of bad
30 * (ch - '9' - 1) is negative if ch <= '9'
31 * ('0' - 1 - ch) is negative if ch >= '0'
32 * we "and" these two values, so the result is negative if ch is in the range
34 * we are only interested in the sign, so we do a shift ">> 8"; note that right
35 * shift of a negative value is implementation-defined, so we cast the
36 * value to (unsigned) before the shift --- we have 0xffffff if ch is in
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| /openbmc/linux/sound/soc/fsl/ |
| H A D | fsl_micfil.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
38 /* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */
53 #define MICFIL_CTRL1_CHEN(ch) BIT(ch) argument
55 /* MICFIL Control Register 2 -- REG_MICFILL_CTRL2 0x04 */
68 /* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */
72 #define MICFIL_STAT_CHXF(ch) BIT(ch) argument
74 /* MICFIL FIFO Control Register -- REG_MICFIL_FIFO_CTRL 0x10 */
77 /* MICFIL FIFO Status Register -- REG_MICFIL_FIFO_STAT 0x14 */
78 #define MICFIL_FIFO_STAT_FIFOX_OVER(ch) BIT(ch) argument
79 #define MICFIL_FIFO_STAT_FIFOX_UNDER(ch) BIT((ch) + 8) argument
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| /openbmc/linux/drivers/gpio/ |
| H A D | gpio-ml-ioh.c | 1 // SPDX-License-Identifier: GPL-2.0-only
38 struct ioh_reg_comn regs[8];
46 * struct ioh_gpio_reg_data - The register store data.
66 * struct ioh_gpio - GPIO private data structure.
74 * @ch: Indicate GPIO channel
85 int ch; member
98 spin_lock_irqsave(&chip->spinlock, flags); in ioh_gpio_set()
99 reg_val = ioread32(&chip->reg->regs[chip->ch].po); in ioh_gpio_set()
105 iowrite32(reg_val, &chip->reg->regs[chip->ch].po); in ioh_gpio_set()
106 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_gpio_set()
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| /openbmc/u-boot/drivers/video/ |
| H A D | ipu_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Porting to u-boot:
10 * (C) Copyright 2005-2009 Freescale Semiconductor, Inc.
17 #define IPU_MCU_T_DEFAULT 8
62 #define DC_EVT_NEW_DATA 8
72 #define DC_EVT_NEW_CHAN_R_0 8
78 #define SW_IPU_RST 8
120 DP_COM_CONF_CSC_DEF_OFFSET = 8,
143 DI_SYNC_NONE = -1,
200 u32 gamma_c_async[8];
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| /openbmc/linux/drivers/clk/berlin/ |
| H A D | berlin2-avpll.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
8 #include <linux/clk-provider.h>
15 #include "berlin2-avpll.h"
19 * VCO with 8 channels each, channel 8 is the odd-one-out and does
29 #define NUM_CHANNELS 8
46 #define VCO_REG0V9_SEL_SHIFT 8
118 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_is_enabled()
119 if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) in berlin2_avpll_vco_is_enabled()
130 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable()
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| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | sdram_common.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
24 * [8] bk_ch0
34 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
36 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
37 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
39 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
41 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
43 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
45 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
47 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
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| /openbmc/linux/drivers/tty/serial/jsm/ |
| H A D | jsm_neo.c | 1 // SPDX-License-Identifier: GPL-2.0+
20 static u32 jsm_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
25 * a non-destructive, read-only location on the Neo card.
27 * In this case, we are reading the DVID (Read-only Device Identification)
32 readb(bd->re_map_membase + 0x8D); in neo_pci_posting_flush()
35 static void neo_set_cts_flow_control(struct jsm_channel *ch) in neo_set_cts_flow_control() argument
38 ier = readb(&ch->ch_neo_uart->ier); in neo_set_cts_flow_control()
39 efr = readb(&ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
41 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n"); in neo_set_cts_flow_control()
51 writeb(0, &ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
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| /openbmc/linux/sound/isa/sb/ |
| H A D | emu8000_callback.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 1999-2000 Takashi Iwai <tiwai@suse.de>
22 static void reset_voice(struct snd_emux *emu, int ch);
39 static void snd_emu8000_tweak_voice(struct snd_emu8000 *emu, int ch);
43 * macro evaluates its args more than once, so changed to upper-case.
74 hw->emu->ops = emu8000_ops; in snd_emu8000_ops_setup()
88 hw = vp->hw; in release_voice()
89 dcysusv = 0x8000 | (unsigned char)vp->reg.parm.modrelease; in release_voice()
90 EMU8000_DCYSUS_WRITE(hw, vp->ch, dcysusv); in release_voice()
91 dcysusv = 0x8000 | (unsigned char)vp->reg.parm.volrelease; in release_voice()
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| /openbmc/linux/sound/pci/emu10k1/ |
| H A D | emu10k1_callback.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
42 * macro evaluates its args more than once, so changed to upper-case.
68 emux->ops = emu10k1_ops; in snd_emu10k1_ops_setup()
87 emu = hw->synth; in snd_emu10k1_synth_get_voice()
92 int ch; in snd_emu10k1_synth_get_voice() local
93 vp = &emu->voices[best[i].voice]; in snd_emu10k1_synth_get_voice()
94 ch = vp->ch; in snd_emu10k1_synth_get_voice()
95 if (ch < 0) { in snd_emu10k1_synth_get_voice()
97 dev_warn(emu->card->dev, in snd_emu10k1_synth_get_voice()
98 "synth_get_voice: ch < 0 (%d) ??", i); in snd_emu10k1_synth_get_voice()
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| /openbmc/linux/drivers/media/pci/solo6x10/ |
| H A D | solo6x10-regs.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2010-2013 Bluecherry, LLC <https://www.bluecherrydvr.com>
17 #include "solo6x10-offsets.h"
34 #define SOLO_DMA_CTRL_REFRESH_CYCLE(n) ((n)<<8)
53 #define SOLO_VCLK_VIN0809_DELAY(n) ((n)<<8)
70 #define SOLO_IRQ_PS2_0 BIT(8)
107 #define SOLO_P2M_CSC_BYTE_REORDER BIT(5) /* BGR -> RGB */
121 #define SOLO_P2M_COMMAND_DONE BIT(8)
135 /* 0:Y[0]<-0(OFF), 1:Y[0]<-1(ON), 2:Y[0]<-G[0], 3:Y[0]<-Bit[15] */
167 #define SOLO_FI_INV_DISP_LIVE(n) ((n)<<8)
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| /openbmc/linux/drivers/media/pci/cx25821/ |
| H A D | cx25821-core.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include "cx25821-sram.h"
16 #include "cx25821-video.h"
19 MODULE_AUTHOR("Shu Lin - Hiep Huynh");
26 static unsigned int card[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET };
243 .irq_bit = 8,
332 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--) { in cx25821_risc_decode()
356 /* PLL-A setting for the Audio Master Clock */ in cx25821_registers_init()
366 /* PLL-B setting for Mobilygen Host Bus Interface */ in cx25821_registers_init()
376 /* PLL-C setting for video upstream channel */ in cx25821_registers_init()
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