1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
38 /* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */
53 #define MICFIL_CTRL1_CHEN(ch)		BIT(ch)  argument
55 /* MICFIL Control Register 2 -- REG_MICFILL_CTRL2 0x04 */
68 /* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */
72 #define MICFIL_STAT_CHXF(ch)		BIT(ch)  argument
74 /* MICFIL FIFO Control Register -- REG_MICFIL_FIFO_CTRL 0x10 */
77 /* MICFIL FIFO Status Register -- REG_MICFIL_FIFO_STAT 0x14 */
78 #define MICFIL_FIFO_STAT_FIFOX_OVER(ch)	BIT(ch)  argument
79 #define MICFIL_FIFO_STAT_FIFOX_UNDER(ch)	BIT((ch) + 8)  argument
81 /* MICFIL DC Remover Control Register -- REG_MICFIL_DC_CTRL */
83 #define MICFIL_DC_CHX_SHIFT(ch)        ((ch) << 1)  argument
84 #define MICFIL_DC_CHX(ch)              GENMASK((((ch) << 1) + 1), ((ch) << 1))  argument
90 /* MICFIL VERID Register -- REG_MICFIL_VERID */
98 /* MICFIL PARAM Register -- REG_MICFIL_PARAM */
107 #define MICFIL_PARAM_FIL_OUT_WIDTH      BIT(8)
113 /* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/
116 #define MICFIL_VAD0_CTRL1_INITT		GENMASK(12, 8)
123 /* MICFIL HWVAD0 Control 2 Register -- REG_MICFIL_VAD0_CTRL2*/
128 #define MICFIL_VAD0_CTRL2_INPGAIN	GENMASK(11, 8)
131 /* MICFIL HWVAD0 Signal CONFIG Register -- REG_MICFIL_VAD0_SCONFIG */
136 /* MICFIL HWVAD0 Noise CONFIG Register -- REG_MICFIL_VAD0_NCONFIG */
141 #define MICFIL_VAD0_NCONFIG_NFILADJ		GENMASK(12, 8)
144 /* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */
146 #define MICFIL_VAD0_ZCD_ZCDADJ		GENMASK(11, 8)
151 /* MICFIL HWVAD0 Status Register - REG_MICFIL_VAD0_STAT */
161 #define MICFIL_OUTPUT_CHANNELS		8
162 #define MICFIL_FIFO_NUM			8
178  * struct fsl_micfil_verid - version id data
188  * struct fsl_micfil_param - parameter data
190  * @hwvad_zcd: HWVAD zero-cross detector is active