Lines Matching +full:8 +full:- +full:ch
1 // SPDX-License-Identifier: Intel
82 tck = t_ck[mrc_params->ddr_speed]; /* Clock in picoseconds */ in prog_ddr_timing_control()
83 tcl = mrc_params->params.cl; /* CAS latency in clocks */ in prog_ddr_timing_control()
86 tras = MCEIL(mrc_params->params.ras, tck); in prog_ddr_timing_control()
88 /* Per JEDEC: tWR=15000ps DDR2/3 from 800-1600 */ in prog_ddr_timing_control()
91 twtr = MCEIL(mrc_params->params.wtr, tck); in prog_ddr_timing_control()
92 trrd = MCEIL(mrc_params->params.rrd, tck); in prog_ddr_timing_control()
94 tfaw = MCEIL(mrc_params->params.faw, tck); in prog_ddr_timing_control()
96 wl = 5 + mrc_params->ddr_speed; in prog_ddr_timing_control()
99 dtr0 |= mrc_params->ddr_speed; in prog_ddr_timing_control()
101 tmp1 = tcl - 5; in prog_ddr_timing_control()
102 dtr0 |= ((tcl - 5) << 12); in prog_ddr_timing_control()
104 dtr0 |= ((trp - 5) << 4); /* 5 bit DRAM Clock */ in prog_ddr_timing_control()
106 dtr0 |= ((trcd - 5) << 8); /* 5 bit DRAM Clock */ in prog_ddr_timing_control()
109 tmp2 = wl - 3; in prog_ddr_timing_control()
110 dtr1 |= (wl - 3); in prog_ddr_timing_control()
112 dtr1 |= ((wl + 4 + twr - 14) << 8); /* Change to tWTP */ in prog_ddr_timing_control()
114 dtr1 |= ((MMAX(trtp, 4) - 3) << 28); /* 4 bit DRAM Clock */ in prog_ddr_timing_control()
116 dtr1 |= ((trrd - 4) << 24); /* 4 bit DRAM Clock */ in prog_ddr_timing_control()
120 dtr1 |= ((tras - 14) << 20); /* 6 bit DRAM Clock */ in prog_ddr_timing_control()
122 dtr1 |= ((((tfaw + 1) >> 1) - 5) << 16);/* 4 bit DRAM Clock */ in prog_ddr_timing_control()
123 /* Set 4 Clock CAS to CAS delay (multi-burst) */ in prog_ddr_timing_control()
129 dtr2 |= (2 << 8); in prog_ddr_timing_control()
139 if (mrc_params->ddr_speed == DDRFREQ_800) { in prog_ddr_timing_control()
141 dtr3 |= ((tcl - 5 + 1) << 8); in prog_ddr_timing_control()
142 } else if (mrc_params->ddr_speed == DDRFREQ_1066) { in prog_ddr_timing_control()
144 dtr3 |= ((tcl - 5 + 1) << 8); in prog_ddr_timing_control()
148 dtr3 |= ((4 + wl + twtr - 11) << 13); in prog_ddr_timing_control()
151 if (mrc_params->ddr_speed == DDRFREQ_800) in prog_ddr_timing_control()
152 dtr3 |= ((MMAX(0, 1 - 1)) << 22); in prog_ddr_timing_control()
154 dtr3 |= ((MMAX(0, 2 - 1)) << 22); in prog_ddr_timing_control()
161 dtr4 |= ((1 + tmp1 - tmp2 + 2) << 8); in prog_ddr_timing_control()
163 dtr4 |= ((1 + tmp1 - tmp2 + 2) << 12); in prog_ddr_timing_control()
211 * impact, however simulator complains if enabled non-existing rank. in prog_decode_before_jedec()
214 if (mrc_params->rank_enables & 1) in prog_decode_before_jedec()
216 if (mrc_params->rank_enables & 2) in prog_decode_before_jedec()
242 mrc_params->rd_odt_value == 0 ? DRMC_ODTMODE : 0); in perform_ddr_reset()
255 uint8_t ch; /* channel counter */ in ddrphy_init() local
259 /* For DDR3 --> 0 == 800, 1 == 1066, 2 == 1333 */ in ddrphy_init()
260 uint8_t speed = mrc_params->ddr_speed & 3; in ddrphy_init()
266 cas = mrc_params->params.cl; in ddrphy_init()
267 cwl = 5 + mrc_params->ddr_speed; in ddrphy_init()
279 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
280 if (mrc_params->channel_enables & (1 << ch)) { in ddrphy_init()
283 CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
287 CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
291 CMDPTRREG + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
299 /* Initialize DQ01, DQ23, CMD, CLK-CTL, COMP modules */ in ddrphy_init()
303 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
304 if (mrc_params->channel_enables & (1 << ch)) { in ddrphy_init()
305 /* DQ01-DQ23 */ in ddrphy_init()
309 /* Analog MUX select - IO2xCLKSEL */ in ddrphy_init()
313 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
317 switch (mrc_params->rd_odt_value) { in ddrphy_init()
336 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
342 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
347 (cas << 8) | (cas << 0); in ddrphy_init()
350 temp -= 0x01010101; in ddrphy_init()
353 temp -= 0x02020202; in ddrphy_init()
356 temp -= 0x03030303; in ddrphy_init()
359 temp -= 0x04040404; in ddrphy_init()
367 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
372 temp = (0x06 << 16) | (0x07 << 8); in ddrphy_init()
375 temp = (0x07 << 16) | (0x08 << 8); in ddrphy_init()
378 temp = (0x09 << 16) | (0x0a << 8); in ddrphy_init()
381 temp = (0x0a << 16) | (0x0b << 8); in ddrphy_init()
389 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
395 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
398 switch (mrc_params->rd_odt_value) { in ddrphy_init()
413 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
419 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
428 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
429 ((cas + 7) << 16) | ((cas - 4) << 8) | in ddrphy_init()
430 ((cwl - 2) << 0), 0x003f1f1f); in ddrphy_init()
434 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
435 ((cas + 7) << 16) | ((cas - 4) << 8) | in ddrphy_init()
436 ((cwl - 2) << 0), 0x003f1f1f); in ddrphy_init()
442 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
447 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
454 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
459 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
460 1 << 8, 1 << 8); in ddrphy_init()
467 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
474 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
477 /* Per-Bit De-Skew Enable */ in ddrphy_init()
481 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
483 /* Per-Bit De-Skew Enable */ in ddrphy_init()
487 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
493 CMDOBSCKEBBCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
498 CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
503 CMDRCOMPODT + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
510 CMDPMDLYREG4 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
518 CMDPMDLYREG3 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
522 CMDPMDLYREG2 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
526 CMDPMDLYREG1 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
530 CMDPMDLYREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
534 CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
535 (0x6 << 8) | (0x1 << 6) | (0x4 << 0), in ddrphy_init()
539 CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
542 /* CLK-CTL */ in ddrphy_init()
544 CCOBSCKEBBCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
548 CCCFGREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
552 CCRCOMPODT + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
553 (0x03 << 8) | (0x03 << 0), 0x00001f1f); in ddrphy_init()
556 CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
561 * - DQ/DQS/DM RON: 32 Ohm in ddrphy_init()
562 * - CTRL/CMD RON: 27 Ohm in ddrphy_init()
563 * - CLK RON: 26 Ohm in ddrphy_init()
567 DQVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
571 CMDVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
575 CLKVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
579 DQSVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
583 CTLVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
588 COMPEN1CH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
594 DQVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
595 (0x32 << 8) | (0x03 << 0), 0x00003f3f); in ddrphy_init()
598 DQSVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
599 (0x32 << 8) | (0x03 << 0), 0x00003f3f); in ddrphy_init()
602 CLKVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
603 (0x0E << 8) | (0x05 << 0), 0x00003f3f); in ddrphy_init()
608 * - DQ/DQS/DM/CLK SR: 4V/ns, in ddrphy_init()
609 * - CTRL/CMD SR: 1.5V/ns in ddrphy_init()
611 temp = (0x0e << 16) | (0x0e << 12) | (0x08 << 8) | in ddrphy_init()
615 DLYSELCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
619 TCOVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
620 (0x05 << 16) | (0x05 << 8) | (0x05 << 0), in ddrphy_init()
624 CCBUFODTCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
625 (0x03 << 8) | (0x03 << 0), in ddrphy_init()
629 COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
636 DQDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
641 DQDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
646 DQDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
651 DQDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
656 DQODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
661 DQODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
666 DQTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
670 DQTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
676 DQSDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
681 DQSDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
686 DQSDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
691 DQSDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
696 DQSODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
701 DQSODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
706 DQSTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
710 DQSTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
716 CLKDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
721 CLKDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
726 CLKDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
731 CLKDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
736 CLKODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
741 CLKODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
746 CLKTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
750 CLKTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
756 CMDDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
761 CMDDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
766 CMDDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
771 CMDDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
778 CTLDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
783 CTLDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
788 CTLDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
793 CTLDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
800 DQTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
805 DQTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
812 DQSTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
817 DQSTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
824 CLKTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
829 CLKTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
836 set_wcmd(ch, ddr_wcmd[PLATFORM_ID]); in ddrphy_init()
838 set_wcmd(ch, ddr_wclk[PLATFORM_ID] + HALF_CLK); in ddrphy_init()
842 if (mrc_params->rank_enables & (1 << rk)) { in ddrphy_init()
843 set_wclk(ch, rk, ddr_wclk[PLATFORM_ID]); in ddrphy_init()
845 set_wctl(ch, rk, ddr_wctl[PLATFORM_ID]); in ddrphy_init()
847 set_wctl(ch, rk, ddr_wclk[PLATFORM_ID] + HALF_CLK); in ddrphy_init()
934 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
935 if (mrc_params->channel_enables & (1 << ch)) { in ddrphy_init()
936 /* DQ01-DQ23 */ in ddrphy_init()
943 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
955 CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
958 /* CLK-CTL */ in ddrphy_init()
960 CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
970 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
971 if (mrc_params->channel_enables & (1 << ch)) { in ddrphy_init()
972 /* DQ01-DQ23 */ in ddrphy_init()
979 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
991 CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
994 /* CLK-CTL */ in ddrphy_init()
996 CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1006 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
1007 if (mrc_params->channel_enables & (1 << ch)) { in ddrphy_init()
1008 /* DQ01-DQ23 */ in ddrphy_init()
1014 (mrc_params->channel_width == X16)) ? in ddrphy_init()
1023 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1030 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1037 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1049 CMDDLLTXCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1058 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
1059 if (mrc_params->channel_enables & (1 << ch)) { in ddrphy_init()
1068 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1074 ECCCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1077 CMDCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1080 CCCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1083 CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1090 CMDCLKALIGNREG1 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1091 (0x18 << 16) | (0x10 << 8) | in ddrphy_init()
1096 CMDCLKALIGNREG2 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1097 (0x10 << 16) | (0x4 << 8) | (0x2 << 4), in ddrphy_init()
1102 CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1105 CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET) & in ddrphy_init()
1112 CMDPTRREG + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1118 COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
1127 COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
1134 CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1139 CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1192 if ((mrc_params->rank_enables & (1 << rank)) == 0) in perform_jedec_init()
1199 (mrc_params->rd_odt_value == 0 ? DRMC_ODTMODE : 0)); in perform_jedec_init()
1203 * BIT[15:11] --> Always "0" in perform_jedec_init()
1204 * BIT[10:09] --> Rtt_WR: want "Dynamic ODT Off" (0) in perform_jedec_init()
1205 * BIT[08] --> Always "0" in perform_jedec_init()
1206 * BIT[07] --> SRT: use sr_temp_range in perform_jedec_init()
1207 * BIT[06] --> ASR: want "Manual SR Reference" (0) in perform_jedec_init()
1208 * BIT[05:03] --> CWL: use oem_tCWL in perform_jedec_init()
1209 * BIT[02:00] --> PASR: want "Full Array" (0) in perform_jedec_init()
1212 wl = 5 + mrc_params->ddr_speed; in perform_jedec_init()
1213 emrs2_cmd |= ((wl - 5) << 9); in perform_jedec_init()
1214 emrs2_cmd |= (mrc_params->sr_temp_range << 13); in perform_jedec_init()
1218 * BIT[15:03] --> Always "0" in perform_jedec_init()
1219 * BIT[02] --> MPR: want "Normal Operation" (0) in perform_jedec_init()
1220 * BIT[01:00] --> MPR_Loc: want "Predefined Pattern" (0) in perform_jedec_init()
1226 * BIT[15:13] --> Always "0" in perform_jedec_init()
1227 * BIT[12:12] --> Qoff: want "Output Buffer Enabled" (0) in perform_jedec_init()
1228 * BIT[11:11] --> TDQS: want "Disabled" (0) in perform_jedec_init()
1229 * BIT[10:10] --> Always "0" in perform_jedec_init()
1230 * BIT[09,06,02] --> Rtt_nom: use rtt_nom_value in perform_jedec_init()
1231 * BIT[08] --> Always "0" in perform_jedec_init()
1232 * BIT[07] --> WR_LVL: want "Disabled" (0) in perform_jedec_init()
1233 * BIT[05,01] --> DIC: use ron_value in perform_jedec_init()
1234 * BIT[04:03] --> AL: additive latency want "0" (0) in perform_jedec_init()
1235 * BIT[00] --> DLL: want "Enable" (0) in perform_jedec_init()
1238 * 00 --> RZQ/6 (40ohm) in perform_jedec_init()
1239 * 01 --> RZQ/7 (34ohm) in perform_jedec_init()
1240 * 1* --> RESERVED in perform_jedec_init()
1243 * 000 --> Disabled in perform_jedec_init()
1244 * 001 --> RZQ/4 ( 60ohm) in perform_jedec_init()
1245 * 010 --> RZQ/2 (120ohm) in perform_jedec_init()
1246 * 011 --> RZQ/6 ( 40ohm) in perform_jedec_init()
1247 * 1** --> RESERVED in perform_jedec_init()
1252 if (mrc_params->ron_value == 0) in perform_jedec_init()
1257 if (mrc_params->rtt_nom_value == 0) in perform_jedec_init()
1259 else if (mrc_params->rtt_nom_value == 1) in perform_jedec_init()
1261 else if (mrc_params->rtt_nom_value == 2) in perform_jedec_init()
1265 mrc_params->mrs1 = emrs1_cmd >> 6; in perform_jedec_init()
1269 * BIT[15:13] --> Always "0" in perform_jedec_init()
1270 * BIT[12] --> PPD: for Quark (1) in perform_jedec_init()
1271 * BIT[11:09] --> WR: use oem_tWR in perform_jedec_init()
1272 * BIT[08] --> DLL: want "Reset" (1, self clearing) in perform_jedec_init()
1273 * BIT[07] --> MODE: want "Normal" (0) in perform_jedec_init()
1274 * BIT[06:04,02] --> CL: use oem_tCAS in perform_jedec_init()
1275 * BIT[03] --> RD_BURST_TYPE: want "Interleave" (1) in perform_jedec_init()
1276 * BIT[01:00] --> BL: want "8 Fixed" (0) in perform_jedec_init()
1278 * 0 --> 16 in perform_jedec_init()
1279 * 1 --> 5 in perform_jedec_init()
1280 * 2 --> 6 in perform_jedec_init()
1281 * 3 --> 7 in perform_jedec_init()
1282 * 4 --> 8 in perform_jedec_init()
1283 * 5 --> 10 in perform_jedec_init()
1284 * 6 --> 12 in perform_jedec_init()
1285 * 7 --> 14 in perform_jedec_init()
1288 * BIT[06:04] use oem_tCAS-4 in perform_jedec_init()
1294 tck = t_ck[mrc_params->ddr_speed]; in perform_jedec_init()
1295 /* Per JEDEC: tWR=15000ps DDR2/3 from 800-1600 */ in perform_jedec_init()
1297 mrs0_cmd |= ((twr - 4) << 15); in perform_jedec_init()
1301 if ((mrc_params->rank_enables & (1 << rank)) == 0) in perform_jedec_init()
1353 uint8_t ch, rk, bl; in restore_timings() local
1354 const struct mrc_timings *mt = &mrc_params->timings; in restore_timings()
1356 for (ch = 0; ch < NUM_CHANNELS; ch++) { in restore_timings()
1359 set_rcvn(ch, rk, bl, mt->rcvn[ch][rk][bl]); in restore_timings()
1360 set_rdqs(ch, rk, bl, mt->rdqs[ch][rk][bl]); in restore_timings()
1361 set_wdqs(ch, rk, bl, mt->wdqs[ch][rk][bl]); in restore_timings()
1362 set_wdq(ch, rk, bl, mt->wdq[ch][rk][bl]); in restore_timings()
1365 set_vref(ch, bl, mt->vref[ch][bl]); in restore_timings()
1368 set_wctl(ch, rk, mt->wctl[ch][rk]); in restore_timings()
1370 set_wcmd(ch, mt->wcmd[ch]); in restore_timings()
1382 uint8_t ch, rk, bl; in default_timings() local
1384 for (ch = 0; ch < NUM_CHANNELS; ch++) { in default_timings()
1387 set_rdqs(ch, rk, bl, 24); in default_timings()
1390 set_vref(ch, bl, 32); in default_timings()
1404 uint8_t ch; /* channel counter */ in rcvn_cal() local
1407 uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1; in rcvn_cal()
1445 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rcvn_cal()
1446 if (mrc_params->channel_enables & (1 << ch)) { in rcvn_cal()
1449 if (mrc_params->rank_enables & (1 << rk)) { in rcvn_cal()
1454 mrc_post_code(0x05, 0x10 + ((ch << 4) | rk)); in rcvn_cal()
1457 /* et hard-coded timing values */ in rcvn_cal()
1459 set_rcvn(ch, rk, bl, ddr_rcvn[PLATFORM_ID]); in rcvn_cal()
1466 ch * DDRIODQ_CH_OFFSET, in rcvn_cal()
1467 0, 1 << 8); in rcvn_cal()
1471 /* 1x CLK domain timing is cas-4 */ in rcvn_cal()
1474 set_rcvn(ch, rk, bl, delay[bl]); in rcvn_cal()
1478 find_rising_edge(mrc_params, delay, ch, rk, true); in rcvn_cal()
1483 set_rcvn(ch, rk, bl, delay[bl]); in rcvn_cal()
1487 temp = sample_dqs(mrc_params, ch, rk, true); in rcvn_cal()
1491 delay[bl] -= FULL_CLK; in rcvn_cal()
1492 set_rcvn(ch, rk, bl, delay[bl]); in rcvn_cal()
1495 training_message(ch, rk, bl); in rcvn_cal()
1509 final_delay[ch][bl] += delay[bl]; in rcvn_cal()
1511 set_rcvn(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); in rcvn_cal()
1517 set_rcvn(ch, rk, bl, delay[bl]); in rcvn_cal()
1526 ch * DDRIODQ_CH_OFFSET, in rcvn_cal()
1527 1 << 8, 1 << 8); in rcvn_cal()
1551 uint8_t ch; /* channel counter */ in wr_level() local
1554 uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1; in wr_level()
1573 * where non-static copies the data onto the stack every time this in wr_level()
1591 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_level()
1592 if (mrc_params->channel_enables & (1 << ch)) { in wr_level()
1595 if (mrc_params->rank_enables & (1 << rk)) { in wr_level()
1600 mrc_post_code(0x06, 0x10 + ((ch << 4) | rk)); in wr_level()
1604 set_wdqs(ch, rk, bl, ddr_wdqs[PLATFORM_ID]); in wr_level()
1605 set_wdq(ch, rk, bl, ddr_wdqs[PLATFORM_ID] - QRTR_CLK); in wr_level()
1632 * Enable Sandy Bridge Mode (WDQ Tri-State) & in wr_level()
1636 DQCTL + DDRIODQ_BL_OFFSET * bl + DDRIODQ_CH_OFFSET * ch, in wr_level()
1643 CCDDR3RESETCTL + DDRIOCCC_CH_OFFSET * ch, in wr_level()
1649 * CLK0 --> RK0 in wr_level()
1650 * CLK1 --> RK1 in wr_level()
1652 delay[bl] = get_wclk(ch, rk); in wr_level()
1654 set_wdqs(ch, rk, bl, delay[bl]); in wr_level()
1658 find_rising_edge(mrc_params, delay, ch, rk, false); in wr_level()
1662 CCDDR3RESETCTL + DDRIOCCC_CH_OFFSET * ch, in wr_level()
1668 DQCTL + DDRIODQ_BL_OFFSET * bl + DDRIODQ_CH_OFFSET * ch, in wr_level()
1680 dram_init_command(DCMD_MRS1(rk, mrc_params->mrs1)); in wr_level()
1688 mrc_post_code(0x06, 0x30 + ((ch << 4) | rk)); in wr_level()
1696 mrc_params->hte_setup = 1; in wr_level()
1700 delay[bl] = get_wdqs(ch, rk, bl) + FULL_CLK; in wr_level()
1701 set_wdqs(ch, rk, bl, delay[bl]); in wr_level()
1704 * (WDQ = WDQS - 32 PI) in wr_level()
1706 set_wdq(ch, rk, bl, (delay[bl] - QRTR_CLK)); in wr_level()
1710 address = get_addr(ch, rk); in wr_level()
1717 mrc_params->hte_setup = 1; in wr_level()
1724 delay[bl] -= FULL_CLK; in wr_level()
1725 set_wdqs(ch, rk, bl, delay[bl]); in wr_level()
1726 /* program WDQ timings based on WDQS (WDQ = WDQS - 32 PI) */ in wr_level()
1727 set_wdq(ch, rk, bl, delay[bl] - QRTR_CLK); in wr_level()
1737 final_delay[ch][bl] += delay[bl]; in wr_level()
1738 set_wdqs(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); in wr_level()
1739 /* program WDQ timings based on WDQS (WDQ = WDQS - 32 PI) */ in wr_level()
1740 set_wdq(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled - QRTR_CLK); in wr_level()
1781 * NOTE: this algorithm assumes the eye curves have a one-to-one relationship,
1782 * meaning for each X the curve has only one Y and vice-a-versa.
1786 uint8_t ch; /* channel counter */ in rd_train() local
1789 uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1; in rd_train()
1819 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rd_train()
1820 if (mrc_params->channel_enables & (1 << ch)) { in rd_train()
1822 if (mrc_params->rank_enables & (1 << rk)) { in rd_train()
1826 set_rdqs(ch, rk, bl, ddr_rdqs[PLATFORM_ID]); in rd_train()
1834 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rd_train()
1835 if (mrc_params->channel_enables & (1 << ch)) { in rd_train()
1837 if (mrc_params->rank_enables & (1 << rk)) { in rd_train()
1842 x_coordinate[L][B][ch][rk][bl] = RDQS_MIN; in rd_train()
1843 x_coordinate[R][B][ch][rk][bl] = RDQS_MAX; in rd_train()
1844 x_coordinate[L][T][ch][rk][bl] = RDQS_MIN; in rd_train()
1845 x_coordinate[R][T][ch][rk][bl] = RDQS_MAX; in rd_train()
1847 y_coordinate[L][B][ch][bl] = VREF_MIN; in rd_train()
1848 y_coordinate[R][B][ch][bl] = VREF_MIN; in rd_train()
1849 y_coordinate[L][T][ch][bl] = VREF_MAX; in rd_train()
1850 y_coordinate[R][T][ch][bl] = VREF_MAX; in rd_train()
1872 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rd_train()
1873 if (mrc_params->channel_enables & (0x1 << ch)) { in rd_train()
1875 if (mrc_params->rank_enables & in rd_train()
1881 set_rdqs(ch, rk, bl, in rd_train()
1882 x_coordinate[side_x][side_y][ch][rk][bl]); in rd_train()
1883 set_vref(ch, bl, in rd_train()
1884 y_coordinate[side_x][side_y][ch][bl]); in rd_train()
1888 address = get_addr(ch, rk); in rd_train()
1891 mrc_params->hte_setup = 1; in rd_train()
1895 /* result[07:00] == failing byte lane (MAX 8) */ in rd_train()
1906 x_coordinate[L][side_y][ch][rk][bl] += RDQS_STEP; in rd_train()
1908 x_coordinate[R][side_y][ch][rk][bl] -= RDQS_STEP; in rd_train()
1911 if ((x_coordinate[L][side_y][ch][rk][bl] > (RDQS_MAX - MIN_RDQS_EYE)) || in rd_train()
1912 (x_coordinate[R][side_y][ch][rk][bl] < (RDQS_MIN + MIN_RDQS_EYE)) || in rd_train()
1913 (x_coordinate[L][side_y][ch][rk][bl] == in rd_train()
1914 x_coordinate[R][side_y][ch][rk][bl])) { in rd_train()
1920 y_coordinate[side_x][B][ch][bl] += VREF_STEP; in rd_train()
1922 y_coordinate[side_x][T][ch][bl] -= VREF_STEP; in rd_train()
1925 if ((y_coordinate[side_x][B][ch][bl] > (VREF_MAX - MIN_VREF_EYE)) || in rd_train()
1926 (y_coordinate[side_x][T][ch][bl] < (VREF_MIN + MIN_VREF_EYE)) || in rd_train()
1927 (y_coordinate[side_x][B][ch][bl] == y_coordinate[side_x][T][ch][bl])) { in rd_train()
1929 training_message(ch, rk, bl); in rd_train()
1933 set_vref(ch, bl, y_coordinate[side_x][side_y][ch][bl]); in rd_train()
1935 x_coordinate[side_x][side_y][ch][rk][bl] = in rd_train()
1941 set_rdqs(ch, rk, bl, x_coordinate[side_x][side_y][ch][rk][bl]); in rd_train()
1956 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rd_train()
1957 if (mrc_params->channel_enables & (1 << ch)) { in rd_train()
1959 if (mrc_params->rank_enables & (1 << rk)) { in rd_train()
1966 "RDQS T/B eye rank%d lane%d : %d-%d %d-%d\n", in rd_train()
1968 x_coordinate[L][T][ch][rk][bl], in rd_train()
1969 x_coordinate[R][T][ch][rk][bl], in rd_train()
1970 x_coordinate[L][B][ch][rk][bl], in rd_train()
1971 x_coordinate[R][B][ch][rk][bl]); in rd_train()
1974 temp1 = (x_coordinate[R][T][ch][rk][bl] + x_coordinate[L][T][ch][rk][bl]) / 2; in rd_train()
1976 temp2 = (x_coordinate[R][B][ch][rk][bl] + x_coordinate[L][B][ch][rk][bl]) / 2; in rd_train()
1978 x_center[ch][rk][bl] = (uint8_t) ((temp1 + temp2) / 2); in rd_train()
1982 "VREF R/L eye lane%d : %d-%d %d-%d\n", in rd_train()
1984 y_coordinate[R][B][ch][bl], in rd_train()
1985 y_coordinate[R][T][ch][bl], in rd_train()
1986 y_coordinate[L][B][ch][bl], in rd_train()
1987 y_coordinate[L][T][ch][bl]); in rd_train()
1990 temp1 = (y_coordinate[R][T][ch][bl] + y_coordinate[R][B][ch][bl]) / 2; in rd_train()
1992 temp2 = (y_coordinate[L][T][ch][bl] + y_coordinate[L][B][ch][bl]) / 2; in rd_train()
1994 y_center[ch][bl] = (uint8_t) ((temp1 + temp2) / 2); in rd_train()
2008 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rd_train()
2009 if (mrc_params->channel_enables & (1 << ch)) { in rd_train()
2011 if (mrc_params->rank_enables & (1 << rk)) { in rd_train()
2014 set_rdqs(ch, rk, bl, x_center[ch][rk][bl] - (MIN_RDQS_EYE / 2)); in rd_train()
2016 set_rdqs(ch, rk, bl, x_center[ch][rk][bl] + (MIN_RDQS_EYE / 2)); in rd_train()
2019 set_vref(ch, bl, y_center[ch][bl] - (MIN_VREF_EYE / 2)); in rd_train()
2021 set_vref(ch, bl, y_center[ch][bl] + (MIN_VREF_EYE / 2)); in rd_train()
2029 mrc_params->hte_setup = 1; in rd_train()
2043 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rd_train()
2044 if (mrc_params->channel_enables & (1 << ch)) { in rd_train()
2046 if (mrc_params->rank_enables & (1 << rk)) { in rd_train()
2054 final_delay[ch][bl] += x_center[ch][rk][bl]; in rd_train()
2055 set_rdqs(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); in rd_train()
2057 set_rdqs(ch, rk, bl, x_center[ch][rk][bl]); in rd_train()
2060 set_vref(ch, bl, y_center[ch][bl]); in rd_train()
2077 * in WR_LVL) +/- 32 PIs (+/- 1/4 CLK) and collapse the eye until all data
2084 uint8_t ch; /* channel counter */ in wr_train() local
2087 uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1; in wr_train()
2111 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_train()
2112 if (mrc_params->channel_enables & (1 << ch)) { in wr_train()
2114 if (mrc_params->rank_enables & (1 << rk)) { in wr_train()
2118 set_wdq(ch, rk, bl, ddr_wdq[PLATFORM_ID]); in wr_train()
2126 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_train()
2127 if (mrc_params->channel_enables & (1 << ch)) { in wr_train()
2129 if (mrc_params->rank_enables & (1 << rk)) { in wr_train()
2135 * WDQ = (WDQS - QRTR_CLK) in wr_train()
2136 * +/- QRTR_CLK in wr_train()
2138 temp = get_wdqs(ch, rk, bl) - QRTR_CLK; in wr_train()
2139 delay[L][ch][rk][bl] = temp - QRTR_CLK; in wr_train()
2140 delay[R][ch][rk][bl] = temp + QRTR_CLK; in wr_train()
2164 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_train()
2165 if (mrc_params->channel_enables & (1 << ch)) { in wr_train()
2167 if (mrc_params->rank_enables & in wr_train()
2172 set_wdq(ch, rk, bl, delay[side][ch][rk][bl]); in wr_train()
2180 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_train()
2181 if (mrc_params->channel_enables & (1 << ch)) { in wr_train()
2183 if (mrc_params->rank_enables & in wr_train()
2186 address = get_addr(ch, rk); in wr_train()
2189 mrc_params->hte_setup = 1; in wr_train()
2193 /* result[07:00] == failing byte lane (MAX 8) */ in wr_train()
2202 delay[L][ch][rk][bl] += WDQ_STEP; in wr_train()
2204 delay[R][ch][rk][bl] -= WDQ_STEP; in wr_train()
2207 if (delay[L][ch][rk][bl] != delay[R][ch][rk][bl]) { in wr_train()
2212 set_wdq(ch, rk, bl, in wr_train()
2213 delay[side][ch][rk][bl]); in wr_train()
2219 training_message(ch, rk, bl); in wr_train()
2234 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_train()
2235 if (mrc_params->channel_enables & (1 << ch)) { in wr_train()
2237 if (mrc_params->rank_enables & (1 << rk)) { in wr_train()
2244 "WDQ eye rank%d lane%d : %d-%d\n", in wr_train()
2246 delay[L][ch][rk][bl], in wr_train()
2247 delay[R][ch][rk][bl]); in wr_train()
2249 temp = (delay[R][ch][rk][bl] + delay[L][ch][rk][bl]) / 2; in wr_train()
2252 final_delay[ch][bl] += temp; in wr_train()
2253 set_wdq(ch, rk, bl, in wr_train()
2254 final_delay[ch][bl] / num_ranks_enabled); in wr_train()
2256 set_wdq(ch, rk, bl, temp); in wr_train()
2276 uint8_t ch, rk, bl; in store_timings() local
2277 struct mrc_timings *mt = &mrc_params->timings; in store_timings()
2279 for (ch = 0; ch < NUM_CHANNELS; ch++) { in store_timings()
2282 mt->rcvn[ch][rk][bl] = get_rcvn(ch, rk, bl); in store_timings()
2283 mt->rdqs[ch][rk][bl] = get_rdqs(ch, rk, bl); in store_timings()
2284 mt->wdqs[ch][rk][bl] = get_wdqs(ch, rk, bl); in store_timings()
2285 mt->wdq[ch][rk][bl] = get_wdq(ch, rk, bl); in store_timings()
2288 mt->vref[ch][bl] = get_vref(ch, bl); in store_timings()
2291 mt->wctl[ch][rk] = get_wctl(ch, rk); in store_timings()
2294 mt->wcmd[ch] = get_wcmd(ch); in store_timings()
2298 mt->ddr_speed = mrc_params->ddr_speed; in store_timings()
2310 if (mrc_params->scrambling_enables == 0) in enable_scrambling()
2316 lfsr = mrc_params->timings.scrambler_seed; in enable_scrambling()
2318 if (mrc_params->boot_mode == BM_COLD) { in enable_scrambling()
2341 mrc_params->timings.scrambler_seed = lfsr; in enable_scrambling()
2374 dpmc0 |= (mrc_params->power_down_disable << 25); in prog_ddr_control()
2381 /* CMDTRIST = 2h - CMD/ADDR are tristated when no valid command */ in prog_ddr_control()
2395 u8 density = mrc_params->params.density; in prog_dra_drb()
2404 if (mrc_params->rank_enables & 1) in prog_dra_drb()
2406 if (mrc_params->rank_enables & 2) in prog_dra_drb()
2408 if (mrc_params->dram_width == X16) { in prog_dra_drb()
2420 drp |= ((density - 1) << 6); in prog_dra_drb()
2421 drp |= ((density - 1) << 11); in prog_dra_drb()
2424 drp |= (mrc_params->address_mode << 14); in prog_dra_drb()
2459 drfc |= (mrc_params->refresh_rate << 12); in change_refresh_period()
2465 dcal |= (3 << 8); /* 63ms */ in change_refresh_period()
2476 * Configure DDRPHY for Auto-Refresh, Periodic Compensations,
2477 * Dynamic Diff-Amp, ZQSPERIOD, Auto-Precharge, CKE Power-Down
2490 * Enable Auto-Refresh, Periodic Compensations, Dynamic Diff-Amp, in set_auto_refresh()
2491 * ZQSPERIOD, Auto-Precharge, CKE Power-Down in set_auto_refresh()
2494 if (mrc_params->channel_enables & (1 << channel)) { in set_auto_refresh()
2499 switch (mrc_params->rd_odt_value) { in set_auto_refresh()
2526 if (mrc_params->rank_enables & (1 << rank)) in set_auto_refresh()
2549 if (mrc_params->ecc_enables == 0) in ecc_enable()
2570 /* Assume 8 bank memory, one bank is gone for ECC */ in ecc_enable()
2571 mrc_params->mem_size -= mrc_params->mem_size / 8; in ecc_enable()
2574 if (mrc_params->boot_mode != BM_S3) { in ecc_enable()
2585 * if error detected it is indicated in mrc_params->status
2598 mrc_params->status = ((result == 0) ? MRC_SUCCESS : MRC_E_MEMTEST); in memory_test()