1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * Porting to u-boot:
10  * (C) Copyright 2005-2009 Freescale Semiconductor, Inc.
17 #define IPU_MCU_T_DEFAULT	8
62 #define DC_EVT_NEW_DATA		8
72 #define DC_EVT_NEW_CHAN_R_0	8
78 #define SW_IPU_RST	8
120 	DP_COM_CONF_CSC_DEF_OFFSET = 8,
143 	DI_SYNC_NONE = -1,
200 	u32 gamma_c_async[8];
212 	u32 gamma_c_sync[8];
301 #define IPU_CONF		(&IPU_CM_REG->conf)
302 #define IPU_SRM_PRI1		(&IPU_CM_REG->srm_pri1)
303 #define IPU_SRM_PRI2		(&IPU_CM_REG->srm_pri2)
304 #define IPU_FS_PROC_FLOW1	(&IPU_CM_REG->fs_proc_flow[0])
305 #define IPU_FS_PROC_FLOW2	(&IPU_CM_REG->fs_proc_flow[1])
306 #define IPU_FS_PROC_FLOW3	(&IPU_CM_REG->fs_proc_flow[2])
307 #define IPU_FS_DISP_FLOW1	(&IPU_CM_REG->fs_disp_flow[0])
308 #define IPU_DISP_GEN		(&IPU_CM_REG->disp_gen)
309 #define IPU_MEM_RST		(&IPU_CM_REG->mem_rst)
310 #define IPU_GPR			(&IPU_CM_REG->gpr)
311 #define IPU_CHA_DB_MODE_SEL(ch)	(&IPU_CM_REG->ch_db_mode_sel[ch / 32])  argument
315 #define IPU_INT_STAT(n)		(&IPU_STAT->int_stat[(n) - 1])
316 #define IPU_CHA_CUR_BUF(ch)	(&IPU_STAT->cur_buf[ch / 32])  argument
317 #define IPU_CHA_BUF0_RDY(ch)	(&IPU_STAT->ch_buf0_rdy[ch / 32])  argument
318 #define IPU_CHA_BUF1_RDY(ch)	(&IPU_STAT->ch_buf1_rdy[ch / 32])  argument
322 #define IPU_INT_CTRL(n)		(&IPU_CM_REG->int_ctrl[(n) - 1])
326 #define IDMAC_CONF		(&IDMAC_REG->conf)
327 #define IDMAC_CHA_EN(ch)	(&IDMAC_REG->ch_en[ch / 32])  argument
328 #define IDMAC_CHA_PRI(ch)	(&IDMAC_REG->ch_pri[ch / 32])  argument
333 #define DI_GENERAL(di)		(&DI_REG(di)->general)
334 #define DI_BS_CLKGEN0(di)	(&DI_REG(di)->bs_clkgen0)
335 #define DI_BS_CLKGEN1(di)	(&DI_REG(di)->bs_clkgen1)
337 #define DI_SW_GEN0(di, gen)	(&DI_REG(di)->sw_gen0[gen - 1])
338 #define DI_SW_GEN1(di, gen)	(&DI_REG(di)->sw_gen1[gen - 1])
339 #define DI_STP_REP(di, gen)	(&DI_REG(di)->stp_rep[(gen - 1) / 2])
340 #define DI_STP_REP9(di)		(&DI_REG(di)->stp_rep9)
341 #define DI_SYNC_AS_GEN(di)	(&DI_REG(di)->sync_as)
342 #define DI_DW_GEN(di, gen)	(&DI_REG(di)->dw_gen[gen])
343 #define DI_DW_SET(di, gen, set)	(&DI_REG(di)->dw_set[gen + 12 * set])
344 #define DI_POL(di)		(&DI_REG(di)->pol)
345 #define DI_SCR_CONF(di)		(&DI_REG(di)->scr_conf)
349 #define DMFC_WR_CHAN		(&DMFC_REG->wr_chan)
350 #define DMFC_WR_CHAN_DEF	(&DMFC_REG->wr_chan_def)
351 #define DMFC_DP_CHAN		(&DMFC_REG->dp_chan)
352 #define DMFC_DP_CHAN_DEF	(&DMFC_REG->dp_chan_def)
353 #define DMFC_GENERAL1		(&DMFC_REG->general[0])
354 #define DMFC_IC_CTRL		(&DMFC_REG->ic_ctrl)
359 #define DC_MAP_CONF_PTR(n)	(&DC_REG->dc_map_ptr[n / 2])
360 #define DC_MAP_CONF_VAL(n)	(&DC_REG->dc_map_val[n / 2])
363 static inline struct ipu_dc_ch *dc_ch_offset(int ch)  in dc_ch_offset()  argument
365 	switch (ch) {  in dc_ch_offset()
369 		return &DC_REG->dc_ch0_1_2[ch];  in dc_ch_offset()
372 		return &DC_REG->dc_ch5_6[ch - 5];  in dc_ch_offset()
373 	case 8:  in dc_ch_offset()
374 		return &DC_REG->dc_ch8;  in dc_ch_offset()
376 		return &DC_REG->dc_ch9;  in dc_ch_offset()
378 		printf("%s: invalid channel %d\n", __func__, ch);  in dc_ch_offset()
384 #define DC_RL_CH(ch, evt)	(&dc_ch_offset(ch)->rl[evt / 2])  argument
386 #define DC_WR_CH_CONF(ch)	(&dc_ch_offset(ch)->wr_ch_conf)  argument
387 #define DC_WR_CH_ADDR(ch)	(&dc_ch_offset(ch)->wr_ch_addr)  argument
392 #define DC_GEN			(&DC_REG->gen)
393 #define DC_DISP_CONF2(disp)	(&DC_REG->disp_conf2[disp])
394 #define DC_STAT			(&DC_REG->stat)
402 #define DP_COM_CONF()		(&DP_REG->com_conf_sync)
403 #define DP_GRAPH_WIND_CTRL()	(&DP_REG->graph_wind_ctrl_sync)
404 #define DP_CSC_A_0()		(&DP_REG->csca_sync[0])
405 #define DP_CSC_A_1()		(&DP_REG->csca_sync[1])
406 #define DP_CSC_A_2()		(&DP_REG->csca_sync[2])
407 #define DP_CSC_A_3()		(&DP_REG->csca_sync[3])
409 #define DP_CSC_0()		(&DP_REG->csc_sync[0])
410 #define DP_CSC_1()		(&DP_REG->csc_sync[1])