Lines Matching +full:8 +full:- +full:ch
1 // SPDX-License-Identifier: GPL-2.0-only
38 struct ioh_reg_comn regs[8];
46 * struct ioh_gpio_reg_data - The register store data.
66 * struct ioh_gpio - GPIO private data structure.
74 * @ch: Indicate GPIO channel
85 int ch; member
98 spin_lock_irqsave(&chip->spinlock, flags); in ioh_gpio_set()
99 reg_val = ioread32(&chip->reg->regs[chip->ch].po); in ioh_gpio_set()
105 iowrite32(reg_val, &chip->reg->regs[chip->ch].po); in ioh_gpio_set()
106 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_gpio_set()
113 return !!(ioread32(&chip->reg->regs[chip->ch].pi) & BIT(nr)); in ioh_gpio_get()
124 spin_lock_irqsave(&chip->spinlock, flags); in ioh_gpio_direction_output()
125 pm = ioread32(&chip->reg->regs[chip->ch].pm); in ioh_gpio_direction_output()
126 pm &= BIT(num_ports[chip->ch]) - 1; in ioh_gpio_direction_output()
128 iowrite32(pm, &chip->reg->regs[chip->ch].pm); in ioh_gpio_direction_output()
130 reg_val = ioread32(&chip->reg->regs[chip->ch].po); in ioh_gpio_direction_output()
135 iowrite32(reg_val, &chip->reg->regs[chip->ch].po); in ioh_gpio_direction_output()
137 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_gpio_direction_output()
148 spin_lock_irqsave(&chip->spinlock, flags); in ioh_gpio_direction_input()
149 pm = ioread32(&chip->reg->regs[chip->ch].pm); in ioh_gpio_direction_input()
150 pm &= BIT(num_ports[chip->ch]) - 1; in ioh_gpio_direction_input()
152 iowrite32(pm, &chip->reg->regs[chip->ch].pm); in ioh_gpio_direction_input()
153 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_gpio_direction_input()
165 for (i = 0; i < 8; i ++, chip++) { in ioh_gpio_save_reg_conf()
166 chip->ioh_gpio_reg.po_reg = in ioh_gpio_save_reg_conf()
167 ioread32(&chip->reg->regs[chip->ch].po); in ioh_gpio_save_reg_conf()
168 chip->ioh_gpio_reg.pm_reg = in ioh_gpio_save_reg_conf()
169 ioread32(&chip->reg->regs[chip->ch].pm); in ioh_gpio_save_reg_conf()
170 chip->ioh_gpio_reg.ien_reg = in ioh_gpio_save_reg_conf()
171 ioread32(&chip->reg->regs[chip->ch].ien); in ioh_gpio_save_reg_conf()
172 chip->ioh_gpio_reg.imask_reg = in ioh_gpio_save_reg_conf()
173 ioread32(&chip->reg->regs[chip->ch].imask); in ioh_gpio_save_reg_conf()
174 chip->ioh_gpio_reg.im0_reg = in ioh_gpio_save_reg_conf()
175 ioread32(&chip->reg->regs[chip->ch].im_0); in ioh_gpio_save_reg_conf()
176 chip->ioh_gpio_reg.im1_reg = in ioh_gpio_save_reg_conf()
177 ioread32(&chip->reg->regs[chip->ch].im_1); in ioh_gpio_save_reg_conf()
179 chip->ioh_gpio_reg.use_sel_reg = in ioh_gpio_save_reg_conf()
180 ioread32(&chip->reg->ioh_sel_reg[i]); in ioh_gpio_save_reg_conf()
191 for (i = 0; i < 8; i ++, chip++) { in ioh_gpio_restore_reg_conf()
192 iowrite32(chip->ioh_gpio_reg.po_reg, in ioh_gpio_restore_reg_conf()
193 &chip->reg->regs[chip->ch].po); in ioh_gpio_restore_reg_conf()
194 iowrite32(chip->ioh_gpio_reg.pm_reg, in ioh_gpio_restore_reg_conf()
195 &chip->reg->regs[chip->ch].pm); in ioh_gpio_restore_reg_conf()
196 iowrite32(chip->ioh_gpio_reg.ien_reg, in ioh_gpio_restore_reg_conf()
197 &chip->reg->regs[chip->ch].ien); in ioh_gpio_restore_reg_conf()
198 iowrite32(chip->ioh_gpio_reg.imask_reg, in ioh_gpio_restore_reg_conf()
199 &chip->reg->regs[chip->ch].imask); in ioh_gpio_restore_reg_conf()
200 iowrite32(chip->ioh_gpio_reg.im0_reg, in ioh_gpio_restore_reg_conf()
201 &chip->reg->regs[chip->ch].im_0); in ioh_gpio_restore_reg_conf()
202 iowrite32(chip->ioh_gpio_reg.im1_reg, in ioh_gpio_restore_reg_conf()
203 &chip->reg->regs[chip->ch].im_1); in ioh_gpio_restore_reg_conf()
205 iowrite32(chip->ioh_gpio_reg.use_sel_reg, in ioh_gpio_restore_reg_conf()
206 &chip->reg->ioh_sel_reg[i]); in ioh_gpio_restore_reg_conf()
213 return chip->irq_base + offset; in ioh_gpio_to_irq()
218 struct gpio_chip *gpio = &chip->gpio; in ioh_gpio_setup()
220 gpio->label = dev_name(chip->dev); in ioh_gpio_setup()
221 gpio->owner = THIS_MODULE; in ioh_gpio_setup()
222 gpio->direction_input = ioh_gpio_direction_input; in ioh_gpio_setup()
223 gpio->get = ioh_gpio_get; in ioh_gpio_setup()
224 gpio->direction_output = ioh_gpio_direction_output; in ioh_gpio_setup()
225 gpio->set = ioh_gpio_set; in ioh_gpio_setup()
226 gpio->dbg_show = NULL; in ioh_gpio_setup()
227 gpio->base = -1; in ioh_gpio_setup()
228 gpio->ngpio = num_port; in ioh_gpio_setup()
229 gpio->can_sleep = false; in ioh_gpio_setup()
230 gpio->to_irq = ioh_gpio_to_irq; in ioh_gpio_setup()
239 int ch; in ioh_irq_type() local
242 int irq = d->irq; in ioh_irq_type()
244 struct ioh_gpio *chip = gc->private; in ioh_irq_type()
246 ch = irq - chip->irq_base; in ioh_irq_type()
247 if (irq <= chip->irq_base + 7) { in ioh_irq_type()
248 im_reg = &chip->reg->regs[chip->ch].im_0; in ioh_irq_type()
249 im_pos = ch; in ioh_irq_type()
251 im_reg = &chip->reg->regs[chip->ch].im_1; in ioh_irq_type()
252 im_pos = ch - 8; in ioh_irq_type()
254 dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n", in ioh_irq_type()
255 __func__, irq, type, ch, im_pos, type); in ioh_irq_type()
257 spin_lock_irqsave(&chip->spinlock, flags); in ioh_irq_type()
278 dev_warn(chip->dev, "%s: unknown type(%dd)", in ioh_irq_type()
288 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr); in ioh_irq_type()
291 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr); in ioh_irq_type()
294 ien = ioread32(&chip->reg->regs[chip->ch].ien); in ioh_irq_type()
295 iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien); in ioh_irq_type()
297 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_irq_type()
305 struct ioh_gpio *chip = gc->private; in ioh_irq_unmask()
307 iowrite32(BIT(d->irq - chip->irq_base), in ioh_irq_unmask()
308 &chip->reg->regs[chip->ch].imaskclr); in ioh_irq_unmask()
314 struct ioh_gpio *chip = gc->private; in ioh_irq_mask()
316 iowrite32(BIT(d->irq - chip->irq_base), in ioh_irq_mask()
317 &chip->reg->regs[chip->ch].imask); in ioh_irq_mask()
323 struct ioh_gpio *chip = gc->private; in ioh_irq_disable()
327 spin_lock_irqsave(&chip->spinlock, flags); in ioh_irq_disable()
328 ien = ioread32(&chip->reg->regs[chip->ch].ien); in ioh_irq_disable()
329 ien &= ~BIT(d->irq - chip->irq_base); in ioh_irq_disable()
330 iowrite32(ien, &chip->reg->regs[chip->ch].ien); in ioh_irq_disable()
331 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_irq_disable()
337 struct ioh_gpio *chip = gc->private; in ioh_irq_enable()
341 spin_lock_irqsave(&chip->spinlock, flags); in ioh_irq_enable()
342 ien = ioread32(&chip->reg->regs[chip->ch].ien); in ioh_irq_enable()
343 ien |= BIT(d->irq - chip->irq_base); in ioh_irq_enable()
344 iowrite32(ien, &chip->reg->regs[chip->ch].ien); in ioh_irq_enable()
345 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_irq_enable()
355 for (i = 0; i < 8; i++, chip++) { in ioh_gpio_handler()
356 reg_val = ioread32(&chip->reg->regs[i].istatus); in ioh_gpio_handler()
359 dev_dbg(chip->dev, in ioh_gpio_handler()
363 &chip->reg->regs[chip->ch].iclr); in ioh_gpio_handler()
364 generic_handle_irq(chip->irq_base + j); in ioh_gpio_handler()
380 gc = devm_irq_alloc_generic_chip(chip->dev, "ioh_gpio", 1, irq_start, in ioh_gpio_alloc_generic_chip()
381 chip->base, handle_simple_irq); in ioh_gpio_alloc_generic_chip()
383 return -ENOMEM; in ioh_gpio_alloc_generic_chip()
385 gc->private = chip; in ioh_gpio_alloc_generic_chip()
386 ct = gc->chip_types; in ioh_gpio_alloc_generic_chip()
388 ct->chip.irq_mask = ioh_irq_mask; in ioh_gpio_alloc_generic_chip()
389 ct->chip.irq_unmask = ioh_irq_unmask; in ioh_gpio_alloc_generic_chip()
390 ct->chip.irq_set_type = ioh_irq_type; in ioh_gpio_alloc_generic_chip()
391 ct->chip.irq_disable = ioh_irq_disable; in ioh_gpio_alloc_generic_chip()
392 ct->chip.irq_enable = ioh_irq_enable; in ioh_gpio_alloc_generic_chip()
394 rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num), in ioh_gpio_alloc_generic_chip()
404 struct device *dev = &pdev->dev; in ioh_gpio_probe()
420 dev_err(dev, "pcim_iomap_regions failed-%d", ret); in ioh_gpio_probe()
427 return -ENOMEM; in ioh_gpio_probe()
430 chip_save = devm_kcalloc(dev, 8, sizeof(*chip), GFP_KERNEL); in ioh_gpio_probe()
432 return -ENOMEM; in ioh_gpio_probe()
436 for (i = 0; i < 8; i++, chip++) { in ioh_gpio_probe()
437 chip->dev = dev; in ioh_gpio_probe()
438 chip->base = base; in ioh_gpio_probe()
439 chip->reg = chip->base; in ioh_gpio_probe()
440 chip->ch = i; in ioh_gpio_probe()
441 spin_lock_init(&chip->spinlock); in ioh_gpio_probe()
443 ret = devm_gpiochip_add_data(dev, &chip->gpio, chip); in ioh_gpio_probe()
451 for (j = 0; j < 8; j++, chip++) { in ioh_gpio_probe()
452 irq_base = devm_irq_alloc_descs(dev, -1, IOH_IRQ_BASE, in ioh_gpio_probe()
459 chip->irq_base = irq_base; in ioh_gpio_probe()
468 ret = devm_request_irq(dev, pdev->irq, ioh_gpio_handler, in ioh_gpio_probe()
485 spin_lock_irqsave(&chip->spinlock, flags); in ioh_gpio_suspend()
487 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_gpio_suspend()
497 spin_lock_irqsave(&chip->spinlock, flags); in ioh_gpio_resume()
498 iowrite32(0x01, &chip->reg->srst); in ioh_gpio_resume()
499 iowrite32(0x00, &chip->reg->srst); in ioh_gpio_resume()
501 spin_unlock_irqrestore(&chip->spinlock, flags); in ioh_gpio_resume()
525 MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");