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/openbmc/linux/Documentation/devicetree/bindings/media/spi/
H A Dsony-cxd2880.txt6 - spi-max-frequency: Maximum bus speed, should be set to <55000000> (55MHz).
17 spi-max-frequency = <55000000>; /* 55MHz */
/openbmc/linux/arch/arm/mach-omap2/
H A Dopp2xxx.h123 /* 2420-PRCM III 532MHz core */
124 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
125 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
126 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
131 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
133 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
134 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
136 #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
141 #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
144 /* 2420-PRCM II 600MHz core */
[all …]
/openbmc/linux/drivers/media/tuners/
H A Dqt1010_priv.h22 07 2b set frequency: 32 MHz scale, n*32 MHz
24 09 10 ? changes every 8/24 MHz; values 1d/1c
25 0a 08 set frequency: 4 MHz scale, n*4 MHz
26 0b 41 ? changes every 2/2 MHz; values 45/45
55 28 55 ?
70 #define QT1010_MIN_FREQ (48 * MHz)
71 #define QT1010_MAX_FREQ (860 * MHz)
72 #define QT1010_OFFSET (1246 * MHz)
/openbmc/linux/drivers/media/dvb-frontends/
H A Dmxl692_defs.h295 MXL_EAGLE_OOB_DEMOD_SYMB_RATE_0_772MHZ, /* ANSI/SCTE 55-2 0.772 MHz */
296 MXL_EAGLE_OOB_DEMOD_SYMB_RATE_1_024MHZ, /* ANSI/SCTE 55-1 1.024 MHz */
297 MXL_EAGLE_OOB_DEMOD_SYMB_RATE_1_544MHZ, /* ANSI/SCTE 55-2 1.544 MHz */
H A Dmxl5xx_defs.h88 MXL_HYDRA_TUNER_ACTIVATE_CMD = 55,
396 MXL_HYDRA_STEP_SIZE_24_XTAL_102_05KHZ, /* 102.05 KHz for 24 MHz XTAL */
397 MXL_HYDRA_STEP_SIZE_24_XTAL_204_10KHZ, /* 204.10 KHz for 24 MHz XTAL */
398 MXL_HYDRA_STEP_SIZE_24_XTAL_306_15KHZ, /* 306.15 KHz for 24 MHz XTAL */
399 MXL_HYDRA_STEP_SIZE_24_XTAL_408_20KHZ, /* 408.20 KHz for 24 MHz XTAL */
401 MXL_HYDRA_STEP_SIZE_27_XTAL_102_05KHZ, /* 102.05 KHz for 27 MHz XTAL */
402 MXL_HYDRA_STEP_SIZE_27_XTAL_204_35KHZ, /* 204.35 KHz for 27 MHz XTAL */
403 MXL_HYDRA_STEP_SIZE_27_XTAL_306_52KHZ, /* 306.52 KHz for 27 MHz XTAL */
404 MXL_HYDRA_STEP_SIZE_27_XTAL_408_69KHZ, /* 408.69 KHz for 27 MHz XTAL */
433 MXL_HYDRA_SEARCH_MAX_OFFSET = 0, /* DMD searches for max freq offset (i.e. 5MHz) */
[all …]
/openbmc/u-boot/include/configs/
H A Dmcx.h51 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
165 "gpio set 55\0" \
202 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
270 48, 49, 50, 51, 52, 53, 54, 55,\
H A Dtam3517-common.h48 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
94 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
175 48, 49, 50, 51, 52, 53, 54, 55,\
255 * bit 48~55 : week of year, from 0.
H A Dtricorder.h46 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
190 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
241 52, 53, 54, 55, 56}
H A Dat91sam9m10g45ek.h17 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
132 48, 49, 50, 51, 52, 53, 54, 55, \
H A Dcorvus.h30 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
132 48, 49, 50, 51, 52, 53, 54, 55, \
/openbmc/linux/arch/powerpc/boot/dts/
H A Dac14xx.dts26 timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
27 bus-frequency = <160000000>; /* 160 MHz csb bus */
28 clock-frequency = <400000000>; /* 400 MHz ppc core */
145 bus-frequency = <80000000>; /* 80 MHz ips bus */
214 at24@55 {
262 54 30 31 38 30 30 33 44 4D 55 0A 0A 00 00 00 10
H A Dcurrituck.dts35 timebase-frequency = <100000000>; // 100Mhz
49 timebase-frequency = <100000000>; // 100Mhz
82 clock-frequency = <200000000>; // 200Mhz
232 0x0 0x0 0x0 0x2 &MPIC 55 0x2 /* int B */
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Drs.h14 * bandwidths <= 80MHz
16 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
37 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
38 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
39 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
40 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
41 * @IWL_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel
122 * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz
123 * @IWL_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz
146 * <nss, channel-width> pair (0 - 80mhz width and below, 1 - 160mhz).
[all …]
/openbmc/linux/drivers/ata/
H A Dpata_hpt37x.c146 55,
595 * @freq: Reported frequency in MHz
598 * and 3 for 66Mhz)
604 return 0; /* 33Mhz slot */ in hpt37x_clock_slot()
606 return 1; /* 40Mhz slot */ in hpt37x_clock_slot()
607 if (freq < 55) in hpt37x_clock_slot()
608 return 2; /* 50Mhz slot */ in hpt37x_clock_slot()
609 return 3; /* 60Mhz slot */ in hpt37x_clock_slot()
688 freq = (fcnt * base) / 192; /* in MHz */ in hpt37x_pci_clock()
695 if (freq < 55) in hpt37x_pci_clock()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dst,nomadik.txt18 i.e. the driver output for the main (~19.2 MHz) chrystal,
96 (55 RESERVED)
/openbmc/u-boot/cmd/
H A Dotp_info.h48 { 7, 2, 1, "CPU Frequency : 800MHz" },
135 { 55, 2, 0, "Boot SPI CRTM size : 0KB" },
136 { 55, 2, 1, "Boot SPI CRTM size : 256KB" },
137 { 55, 2, 2, "Boot SPI CRTM size : 512KB" },
138 { 55, 2, 3, "Boot SPI CRTM size : 1024KB" },
170 { 7, 3, 4, "CPU Frequency : 800MHz" },
171 { 7, 3, 5, "CPU Frequency : 800MHz" },
172 { 7, 3, 6, "CPU Frequency : 800MHz" },
173 { 7, 3, 7, "CPU Frequency : 800MHz" },
264 { 55, 2, 0, "Boot SPI CRTM size : 0KB" },
[all …]
/openbmc/u-boot/board/hisilicon/hikey/
H A DREADME7 * 1GB 800MHz LPDDR3 DRAM
125 INFO: succeed to set ddrc 150mhz
127 INFO: succeed to set ddrc 266mhz
129 INFO: succeed to set ddrc 400mhz
131 INFO: succeed to set ddrc 533mhz
133 INFO: succeed to set ddrc 800mhz
211 U-Boot 2018.09-rc1 (Aug 22 2018 - 14:55:49 +0530)hikey
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dmarvell,xenon-sdhci.yaml124 Only available when bus frequency lower than 55MHz in SDR mode.
227 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
269 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam3517.dtsi33 * AM3517 TRM only lists 600MHz @ 1.2V, but omap36xx
34 * appear to operate at 300MHz as well. Since AM3517 only
120 dmas = <&sdma 55 &sdma 54>;
/openbmc/linux/drivers/net/wireless/ath/wcn36xx/
H A Dtxrx.c51 { 55, 2, RX_ENC_LEGACY, 0, RATE_INFO_BW_20 },
57 { 55, 2, RX_ENC_LEGACY, RX_ENC_FLAG_SHORTPRE, RATE_INFO_BW_20 },
134 /* 11ac 20 MHz 800ns GI MCS 0-8 */
156 /* 11ac 20 MHz 400ns SGI MCS 6-8 */
166 /* 11ac 40 MHz 800ns GI MCS 0-9 */
187 /* 11ac 40 MHz 400ns SGI MCS 5-7 */
195 /* 11ac 40 MHz 400ns SGI MCS 5-7 */
202 /* 11ac 80 MHz 800ns GI MCS 0-7 */
215 /* 11ac 80 MHz 800 ns GI MCS 8-9 */
228 /* 11ac 80 MHz 400 ns SGI MCS 6-7 */
[all …]
/openbmc/u-boot/drivers/phy/marvell/
H A Dcomphy_a3700.c212 /* 40 MHz */ in comphy_pcie_power_up()
215 /* 25 MHz */ in comphy_pcie_power_up()
241 /* Wait for > 55 us to allow PCLK be enabled */ in comphy_pcie_power_up()
294 /* 40 MHz */ in comphy_sata_power_up()
297 /* 20 MHz */ in comphy_sata_power_up()
317 /* Wait for > 55 us to allow PLL be enabled */ in comphy_sata_power_up()
425 /* 40 MHz */ in comphy_usb3_power_up()
429 /* 25 MHz */ in comphy_usb3_power_up()
481 /* Wait for > 55 us to allow PCLK be enabled */ in comphy_usb3_power_up()
546 * 0. Setup PLL. 40MHz clock uses defaults. in comphy_usb2_power_up()
[all …]
/openbmc/linux/drivers/usb/dwc3/
H A Ddwc3-octeon.c49 * [55:53] = modules -1
52 # define USBDRD_UCTL_CTL_SSC_REF_CLK_SEL GENMASK_ULL(55, 47)
54 * 0x19 = 100MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
55 * 0x28 = 125MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
56 * 0x32 = 50MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
68 * 0x1 = DLMC_REF_CLK* is 125MHz
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_aldebaran.h93 #define FEATURE_SPARE_55_BIT 55
331 uint16_t GfxclkFmax; // In MHz
332 uint16_t GfxclkFmin; // In MHz
333 uint16_t GfxclkFidle; // In MHz
334 uint16_t GfxclkFinit; // In MHz
341 uint16_t GFX_Guardband_Freq[8]; // MHz [unsigned]
346 uint16_t SOC_Guardband_Freq[8]; // MHz [unsigned]
/openbmc/linux/Documentation/fb/
H A Dintel810.rst23 - Intel 815 Internal graphics only, 100Mhz FSB
191 append="video=i810fb:vram:2,xres:1024,yres:768,bpp:8,hsync1:30,hsync2:55, \
219 modprobe i810fb vram=2 xres=1024 bpp=8 hsync1=30 hsync2=55 vsync1=50 \
224 options i810fb vram=2 xres=1024 bpp=16 hsync1=30 hsync2=55 vsync1=50 \
/openbmc/u-boot/arch/arm/include/asm/arch-omap3/
H A Dmem.h110 /* Hynix part of Overo (165MHz optimized) 6.06ns */
136 /* Hynix part of AM/DM37xEVM (200MHz optimized) */
162 /* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
188 /* Micron part of 3430 EVM (165MHz optimized) 6.06ns */
225 /* Micron part (200MHz optimized) 5 ns */
251 /* Samsung K4X51163PG - FGC6 (165MHz optimized) 6.06ns - from 2010.90 src */
294 /* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
323 /* NUMONYX part of IGEP v2 (200MHz optimized) 5 ns */
331 #define NUMONYX_TRC_200 11 /* 55/5 = 11 */

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