1ef6eb322SLinus WalleijST Microelectronics Nomadik SRC System Reset and Control 2ef6eb322SLinus Walleij 3ef6eb322SLinus WalleijThis binding uses the common clock binding: 4ef6eb322SLinus WalleijDocumentation/devicetree/bindings/clock/clock-bindings.txt 5ef6eb322SLinus Walleij 6ef6eb322SLinus WalleijThe Nomadik SRC controller is responsible of controlling chrystals, 7ef6eb322SLinus WalleijPLLs and clock gates. 8ef6eb322SLinus Walleij 9ef6eb322SLinus WalleijRequired properties for the SRC node: 10ef6eb322SLinus Walleij- compatible: must be "stericsson,nomadik-src" 11ef6eb322SLinus Walleij- reg: must contain the SRC register base and size 12ef6eb322SLinus Walleij 13ef6eb322SLinus WalleijOptional properties for the SRC node: 14ef6eb322SLinus Walleij- disable-sxtalo: if present this will disable the SXTALO 15ef6eb322SLinus Walleij i.e. the driver output for the slow 32kHz chrystal, if the 16ef6eb322SLinus Walleij board has its own circuitry for providing this oscillator 17ef6eb322SLinus Walleij- disable-mxtal: if present this will disable the MXTALO, 18ef6eb322SLinus Walleij i.e. the driver output for the main (~19.2 MHz) chrystal, 19ef6eb322SLinus Walleij if the board has its own circuitry for providing this 203999debeSStefan Huber oscillator 21ef6eb322SLinus Walleij 22ef6eb322SLinus Walleij 23ef6eb322SLinus WalleijPLL nodes: these nodes represent the two PLLs on the system, 24ef6eb322SLinus Walleijwhich should both have the main chrystal, represented as a 25ef6eb322SLinus Walleijfixed frequency clock, as parent. 26ef6eb322SLinus Walleij 27ef6eb322SLinus WalleijRequired properties for the two PLL nodes: 28ef6eb322SLinus Walleij- compatible: must be "st,nomadik-pll-clock" 29ef6eb322SLinus Walleij- clock-cells: must be 0 30ef6eb322SLinus Walleij- clock-id: must be 1 or 2 for PLL1 and PLL2 respectively 31ef6eb322SLinus Walleij- clocks: this clock will have main chrystal as parent 32ef6eb322SLinus Walleij 33ef6eb322SLinus Walleij 34ef6eb322SLinus WalleijHCLK nodes: these represent the clock gates on individual 35ef6eb322SLinus Walleijlines from the HCLK clock tree and the gate for individual 36ef6eb322SLinus Walleijlines from the PCLK clock tree. 37ef6eb322SLinus Walleij 38ef6eb322SLinus WalleijRequires properties for the HCLK nodes: 39ef6eb322SLinus Walleij- compatible: must be "st,nomadik-hclk-clock" 40ef6eb322SLinus Walleij- clock-cells: must be 0 41ef6eb322SLinus Walleij- clock-id: must be the clock ID from 0 to 63 according to 42ef6eb322SLinus Walleij this table: 43ef6eb322SLinus Walleij 44ef6eb322SLinus Walleij 0: HCLKDMA0 45ef6eb322SLinus Walleij 1: HCLKSMC 46ef6eb322SLinus Walleij 2: HCLKSDRAM 47ef6eb322SLinus Walleij 3: HCLKDMA1 48ef6eb322SLinus Walleij 4: HCLKCLCD 49ef6eb322SLinus Walleij 5: PCLKIRDA 50ef6eb322SLinus Walleij 6: PCLKSSP 51ef6eb322SLinus Walleij 7: PCLKUART0 52ef6eb322SLinus Walleij 8: PCLKSDI 53ef6eb322SLinus Walleij 9: PCLKI2C0 54ef6eb322SLinus Walleij 10: PCLKI2C1 55ef6eb322SLinus Walleij 11: PCLKUART1 56ef6eb322SLinus Walleij 12: PCLMSP0 57ef6eb322SLinus Walleij 13: HCLKUSB 58ef6eb322SLinus Walleij 14: HCLKDIF 59ef6eb322SLinus Walleij 15: HCLKSAA 60ef6eb322SLinus Walleij 16: HCLKSVA 61ef6eb322SLinus Walleij 17: PCLKHSI 62ef6eb322SLinus Walleij 18: PCLKXTI 63ef6eb322SLinus Walleij 19: PCLKUART2 64ef6eb322SLinus Walleij 20: PCLKMSP1 65ef6eb322SLinus Walleij 21: PCLKMSP2 66ef6eb322SLinus Walleij 22: PCLKOWM 67ef6eb322SLinus Walleij 23: HCLKHPI 68ef6eb322SLinus Walleij 24: PCLKSKE 69ef6eb322SLinus Walleij 25: PCLKHSEM 70ef6eb322SLinus Walleij 26: HCLK3D 71ef6eb322SLinus Walleij 27: HCLKHASH 72ef6eb322SLinus Walleij 28: HCLKCRYP 73ef6eb322SLinus Walleij 29: PCLKMSHC 74ef6eb322SLinus Walleij 30: HCLKUSBM 75ef6eb322SLinus Walleij 31: HCLKRNG 76ef6eb322SLinus Walleij (32, 33, 34, 35 RESERVED) 77ef6eb322SLinus Walleij 36: CLDCLK 78ef6eb322SLinus Walleij 37: IRDACLK 79ef6eb322SLinus Walleij 38: SSPICLK 80ef6eb322SLinus Walleij 39: UART0CLK 81ef6eb322SLinus Walleij 40: SDICLK 82ef6eb322SLinus Walleij 41: I2C0CLK 83ef6eb322SLinus Walleij 42: I2C1CLK 84ef6eb322SLinus Walleij 43: UART1CLK 85ef6eb322SLinus Walleij 44: MSPCLK0 86ef6eb322SLinus Walleij 45: USBCLK 87ef6eb322SLinus Walleij 46: DIFCLK 88ef6eb322SLinus Walleij 47: IPI2CCLK 89ef6eb322SLinus Walleij 48: IPBMCCLK 90ef6eb322SLinus Walleij 49: HSICLKRX 91ef6eb322SLinus Walleij 50: HSICLKTX 92ef6eb322SLinus Walleij 51: UART2CLK 93ef6eb322SLinus Walleij 52: MSPCLK1 94ef6eb322SLinus Walleij 53: MSPCLK2 95ef6eb322SLinus Walleij 54: OWMCLK 96ef6eb322SLinus Walleij (55 RESERVED) 97ef6eb322SLinus Walleij 56: SKECLK 98ef6eb322SLinus Walleij (57 RESERVED) 99ef6eb322SLinus Walleij 58: 3DCLK 100ef6eb322SLinus Walleij 59: PCLKMSP3 101ef6eb322SLinus Walleij 60: MSPCLK3 102ef6eb322SLinus Walleij 61: MSHCCLK 103ef6eb322SLinus Walleij 62: USBMCLK 104ef6eb322SLinus Walleij 63: RNGCCLK 105