| /openbmc/qemu/tests/qemu-iotests/ |
| H A D | 036 | 44 # This tests qcow2-specific low-level functionality
54 echo === Image with unknown incompatible feature bit ===
57 $PYTHON qcow2.py "$TEST_IMG" set-feature-bit incompatible 63
60 $PYTHON qcow2.py "$TEST_IMG" del-header-ext 0x6803f857
62 $PYTHON qcow2.py "$TEST_IMG" dump-header-exts
65 # With feature table containing bit 63
66 printf "\x00\x3f%s" "Test feature" | $PYTHON qcow2.py "$TEST_IMG" add-header-ext-stdio 0x6803f857
73 $PYTHON qcow2.py "$TEST_IMG" set-feature-bit incompatible 61
74 $PYTHON qcow2.py "$TEST_IMG" set-feature-bit incompatible 62
75 $PYTHON qcow2.py "$TEST_IMG" set-feature-bit incompatible 63
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| /openbmc/linux/Documentation/core-api/ |
| H A D | packing.rst | 6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
15 definitions from the hardware documentation into bit field indices for the
18 (sometimes even 64 bit ones). This creates the inconvenience of having to
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
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| /openbmc/qemu/hw/riscv/ |
| H A D | riscv-iommu-bits.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2022-2023 Rivos Inc.
4 * Copyright © 2023 FORTH-ICS/CARV
5 * Copyright © 2023 RISC-V IOMMU Task Group
7 * RISC-V IOMMU - Register Layout and Data Structures.
10 * https://github.com/riscv-non-isa/riscv-iommu
19 #define GENMASK_ULL(h, l) (((~0ULL) >> (63 - (h) + (l))) << (l))
23 * struct riscv_iommu_fq_record - Fault/Event Queue Record
37 #define RISCV_IOMMU_FQ_HDR_DID GENMASK_ULL(63, 40)
40 * struct riscv_iommu_pq_record - PCIe Page Request record
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|
| /openbmc/qemu/docs/specs/ |
| H A D | ppc-spapr-numa.rst | 12 --------------------------------------------
19 bit 0 of byte 5 of the ibm,architecture-vec-5 property. The format with
20 bit 0 equal to zero is deprecated. The current format, with the bit 0
28 Mem M1 ---- Proc P1 |
29 ----------------- | Socket S1 ---|
32 Mem M2 ---- Proc P2 | |
33 ----------------- | Socket S2 ---|
46 Relative Performance Distance and ibm,associativity-reference-points
47 --------------------------------------------------------------------
49 The ibm,associativity-reference-points property is an array that is used
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| /openbmc/linux/arch/alpha/kernel/ |
| H A D | sys_sable.c | 1 // SPDX-License-Identifier: GPL-2.0
9 * Code supporting the Sable, Sable-Gamma, and Lynx systems.
39 /* Note mask bit is true for DISABLED irqs. */
42 void (*update_irq_hw)(unsigned long bit, unsigned long mask);
43 void (*ack_irq_hw)(unsigned long bit);
55 * For SABLE, which is really baroque, we manage 40 IRQ's, but the
58 * 0-7 (char at 536)
59 * 8-15 (char at 53a)
60 * 16-23 (char at 53c)
64 * Bit Meaning Kernel IRQ
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|
| H A D | sys_wildfire.c | 1 // SPDX-License-Identifier: GPL-2.0
41 int qbbno = (irq >> 8) & (WILDFIRE_MAX_QBB - 1); in wildfire_update_irq_hw()
42 int pcano = (irq >> 6) & (WILDFIRE_PCA_PER_QBB - 1); in wildfire_update_irq_hw()
49 " got irq %d for non-existent PCA %d" in wildfire_update_irq_hw()
57 enable0 = (unsigned long *) &pca->pca_int[0].enable; /* ??? */ in wildfire_update_irq_hw()
72 enable0 = (unsigned long *) &pca->pca_int[0].enable; in wildfire_init_irq_hw()
73 enable1 = (unsigned long *) &pca->pca_int[1].enable; in wildfire_init_irq_hw()
74 enable2 = (unsigned long *) &pca->pca_int[2].enable; in wildfire_init_irq_hw()
75 enable3 = (unsigned long *) &pca->pca_int[3].enable; in wildfire_init_irq_hw()
77 target0 = (unsigned long *) &pca->pca_int[0].target; in wildfire_init_irq_hw()
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| /openbmc/linux/arch/powerpc/platforms/ |
| H A D | Kconfig.cputype | 1 # SPDX-License-Identifier: GPL-2.0
7 bool "64-bit kernel"
10 This option selects whether a 32-bit or a 64-bit kernel
18 There are five families of 32 bit PowerPC chips supported.
46 config 40x
47 bool "AMCC 40x"
85 There are two families of 64 bit PowerPC chips supported.
198 bool "40x family"
199 depends on 40x
282 default "-mtune=power10" if $(cc-option,-mtune=power10)
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| /openbmc/linux/tools/testing/selftests/bpf/progs/ |
| H A D | verifier_spill_fill.c | 1 // SPDX-License-Identifier: GPL-2.0
21 *(u64*)(r10 - 8) = r1; \ in __retval()
23 r2 = *(u64*)(r10 - 8); \ in __retval()
38 *(u64*)(r10 - 8) = r6; \ in valid_spill_fill_skb_mark()
39 r0 = *(u64*)(r10 - 8); \ in valid_spill_fill_skb_mark()
55 *(u64*)(r10 - 8) = r1; \ in spill_fill_ptr_to_mem()
65 *(u64*)(r10 - 8) = r6; \ in spill_fill_ptr_to_mem()
67 r7 = *(u64*)(r10 - 8); \ in spill_fill_ptr_to_mem()
93 *(u64*)(r10 - 8) = r1; \ in with_invalid_reg_offset_0()
129 *(u64*)(r10 - 8) = r1; \ in __flag()
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| /openbmc/linux/arch/mips/loongson64/ |
| H A D | dma.c | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/dma-direct.h>
9 /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from in phys_to_dma()
10 * Loongson-3's 48bit address space and embed it into 40bit */ in phys_to_dma()
18 /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from in dma_to_phys()
19 * Loongson-3's 48bit address space and embed it into 40bit */ in dma_to_phys()
|
| /openbmc/linux/drivers/mtd/nand/raw/ |
| H A D | nand_ids.c | 1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
43 SZ_8K, SZ_4K, SZ_1M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },
44 {"TC58NVG6D2 64G 3.3V 8-bit",
46 SZ_8K, SZ_8K, SZ_2M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },
47 {"SDTNQGAMA 64G 3.3V 8-bit",
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| /openbmc/linux/arch/arm/mach-ep93xx/ |
| H A D | timer-ep93xx.c | 1 // SPDX-License-Identifier: GPL-2.0
17 * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
18 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
19 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
20 * is free-running, and can't generate interrupts.
23 * most common values of HZ divide 508 kHz nicely. We pick the 32 bit
29 * a stable 40 bit time base.
116 evt->event_handler(evt); in ep93xx_timer_interrupt()
130 EP93XX_TIMER4_RATE, 200, 40, in ep93xx_timer_init()
132 sched_clock_register(ep93xx_read_sched_clock, 40, in ep93xx_timer_init()
|
| /openbmc/linux/arch/arm/boot/dts/intel/pxa/ |
| H A D | pxa3xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \
9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
18 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
19 (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) : \
20 (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) : \
21 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
23 (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) : \
33 (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) : \
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| /openbmc/linux/Documentation/powerpc/ |
| H A D | associativity.rst | 9 are represented as being members of a sub-grouping domain. This performance
17 Hypervisor indicates the type/form of associativity used via "ibm,architecture-vec-5 property".
18 Bit 0 of byte 5 in the "ibm,architecture-vec-5" property indicates usage of Form 0 or Form 1.
20 bit 2 of byte 5 in the "ibm,architecture-vec-5" property is used.
23 ------
27 ------
28 With Form 1 a combination of ibm,associativity-reference-points, and ibm,associativity
34 The “ibm,associativity-reference-points” property contains a list of one or more numbers
43 if they belong to the same higher-level domains. For mismatch at every higher
48 -------
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| /openbmc/u-boot/drivers/mtd/nand/raw/ |
| H A D | nand_ids.c | 28 LEGACY_ID_NAND("NAND 1MiB 5V 8-bit", 0x6e, 1, SZ_4K, SP_OPTIONS),
29 LEGACY_ID_NAND("NAND 2MiB 5V 8-bit", 0x64, 2, SZ_4K, SP_OPTIONS),
30 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS),
31 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS),
32 LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS),
33 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS),
35 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xe6, 8, SZ_8K, SP_OPTIONS),
42 {"TC58NVG0S3E 1G 3.3V 8-bit",
46 {"TC58NVG2S0F 4G 3.3V 8-bit",
49 {"TC58NVG2S0H 4G 3.3V 8-bit",
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| /openbmc/linux/arch/x86/lib/ |
| H A D | csum-partial_64.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * arch/x86_64/lib/csum-partial.c
6 * in an architecture-specific manner due to speed.
12 #include <asm/word-at-a-time.h>
35 * Returns a 32bit checksum.
41 * checksums on IPv6 headers (40 bytes) and other small parts.
42 * it's best to have buff aligned on a 64-bit boundary
48 /* Do two 40-byte chunks in parallel to get better ILP */ in csum_partial()
53 temp64_2 = update_csum_40b(temp64_2, buff + 40); in csum_partial()
55 len -= 80; in csum_partial()
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| /openbmc/linux/arch/mips/include/asm/octeon/ |
| H A D | cvmx.h | 7 * Copyright (c) 2003-2017 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
42 /* These macros for use when using 32 bit pointers. */
56 #include <asm/octeon/cvmx-asm.h>
57 #include <asm/octeon/cvmx-packet.h>
58 #include <asm/octeon/cvmx-sysinfo.h>
60 #include <asm/octeon/cvmx-ciu-defs.h>
61 #include <asm/octeon/cvmx-ciu3-defs.h>
62 #include <asm/octeon/cvmx-gpio-defs.h>
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| /openbmc/linux/arch/powerpc/include/asm/nohash/32/ |
| H A D | pte-40x.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 * At present, all PowerPC 400-class processors share a similar TLB
9 * 64-entry, fully-associative TLB which is maintained totally under
11 * hardware-managed, 4-entry, fully-associative TLB which serves as a
15 * There are several potential gotchas here. The 40x hardware TLBLO
23 * - bits 20 and 21 must be cleared, because we use 4k pages (40x can
26 * - We use only zones 0 (for kernel pages) and 1 (for user pages)
27 * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
28 * miss handler. Bit 27 is PAGE_USER, thus selecting the correct
30 * - PRESENT *must* be in the bottom two bits because swap PTEs
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| /openbmc/u-boot/drivers/pinctrl/ |
| H A D | pinctrl-sti.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
28 /* User-frendly defines for Pin Direction */
60 int alt = pin_desc->alt; in sti_alternate_select()
61 int bank = pin_desc->bank; in sti_alternate_select()
62 int pin = pin_desc->pin; in sti_alternate_select()
64 sysconfreg = (unsigned long *)plat->regmap->ranges[0].start; in sti_alternate_select()
71 sysconfreg += bank - 10; in sti_alternate_select()
74 sysconfreg += bank - 30; in sti_alternate_select()
76 case 40 ... 42: /* in "FLASH Bank" */ in sti_alternate_select()
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| /openbmc/u-boot/drivers/phy/marvell/ |
| H A D | comphy_a3700.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Marvell International Ltd.
53 /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */
64 /* 40M1G25 mode init data */
67 /*-----------------------------------------------------------*/
77 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */
144 for (timeout = PLL_LOCK_TIMEOUT; timeout > 0; timeout--) { in comphy_poll_reg()
146 rval = readw(addr); /* 16 bit */ in comphy_poll_reg()
148 rval = readl(addr) ; /* 32 bit */ in comphy_poll_reg()
177 * 2. Select 20 bit SERDES interface. in comphy_pcie_power_up()
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| /openbmc/linux/drivers/staging/fbtft/ |
| H A D | fb_hx8353d.c | 1 // SPDX-License-Identifier: GPL-2.0+
18 #define DEFAULT_GAMMA "50 77 40 08 BF 00 03 0F 00 01 73 00 72 03 B0 0F 08 00 0F"
22 par->fbtftops.reset(par); in init_display()
43 /* SLPOUT - Sleep out & booster on */ in init_display()
47 /* DISPON - Display On */ in init_display()
53 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, in init_display()
56 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, in init_display()
59 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62); in init_display()
76 #define my BIT(7)
77 #define mx BIT(6)
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| /openbmc/linux/Documentation/devicetree/bindings/ufs/ |
| H A D | snps,tc-dwc-g210.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ufs/snps,tc-dwc-g210.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Li Wei <liwei213@huawei.com>
18 - snps,dwc-ufshcd-1.40a
20 - compatible
23 - $ref: ufs-common.yaml
28 - enum:
29 - snps,g210-tc-6.00-20bit
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| /openbmc/linux/drivers/net/ethernet/microchip/sparx5/ |
| H A D | sparx5_netdev.c | 1 // SPDX-License-Identifier: GPL-2.0+
12 /* The IFH bit position of the first VSTAX bit. This is because the
13 * VSTAX bit positions in Data sheet is starting from zero.
21 /* Max width is 5 bytes - 40 bits. In worst case this will
22 * spread over 6 bytes - 48 bits
24 compiletime_assert(width <= 40, \
25 "Unsupported width, must be <= 40"); \
32 /* Calculate the Start IFH byte position of this IFH bit position */ in __ifh_encode_bitfield()
33 u32 byte = (35 - (pos / 8)); in __ifh_encode_bitfield()
34 /* Calculate the Start bit position in the Start IFH byte */ in __ifh_encode_bitfield()
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| /openbmc/linux/drivers/net/wireless/marvell/mwifiex/ |
| H A D | cfp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2011-2020 NXP
66 /* LGI 40M */
70 /* SGI 40M */
101 /* LG 40M */
105 /* SG 40M */
134 /* LG 40M */
138 /* SG 40M */
195 /* 20M: bw=0, 40M: bw=1, 80M: bw=2, 160M: bw=3 */ in mwifiex_index_to_acs_data_rate()
202 rate = ac_mcs_rate_nss2[2 * (3 - bw) + gi][mcs_index]; in mwifiex_index_to_acs_data_rate()
[all …]
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| /openbmc/linux/drivers/net/ethernet/intel/ice/ |
| H A D | ice_ethtool.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
21 * Array index corresponds to HW PHY type bit, see
56 [30] = ICE_PHY_TYPE(40GB, 40000baseCR4_Full),
57 [31] = ICE_PHY_TYPE(40GB, 40000baseSR4_Full),
58 [32] = ICE_PHY_TYPE(40GB, 40000baseLR4_Full),
59 [33] = ICE_PHY_TYPE(40GB, 40000baseKR4_Full),
60 [34] = ICE_PHY_TYPE(40GB, 40000baseSR4_Full),
61 [35] = ICE_PHY_TYPE(40GB, 40000baseCR4_Full),
66 [40] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full),
93 * Array index corresponds to HW PHY type bit, see
|
| /openbmc/linux/drivers/net/ppp/ |
| H A D | ppp_mppe.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 #define MPPE_MAX_KEY_LEN 16 /* largest key length (128-bit) */
6 #define MPPE_OPT_40 0x01 /* 40 bit */
7 #define MPPE_OPT_128 0x02 /* 128 bit */
10 #define MPPE_OPT_56 0x08 /* 56 bit */
19 * names above since C and H are the same bit. We could do a u_int32
25 #define MPPE_L_BIT 0x20 /* 40-bit */
26 #define MPPE_S_BIT 0x40 /* 128-bit */
27 #define MPPE_M_BIT 0x80 /* 56-bit, not supported */
30 /* Does not include H bit; used for least significant octet only. */
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