nohash/32/pte-40x.h

1 /* SPDX-License-Identifier: GPL-2.0 */
7  * At present, all PowerPC 400-class processors share a similar TLB
9  * 64-entry, fully-associative TLB which is maintained totally under
11  * hardware-managed, 4-entry, fully-associative TLB which serves as a
15  * There are several potential gotchas here.  The 40x hardware TLBLO
23  * - bits 20 and 21 must be cleared, because we use 4k pages (40x can
26  * - We use only zones 0 (for kernel pages) and 1 (for user pages)
27  *   of the 16 available.  Bit 24-26 of the TLB are cleared in the TLB
28  *   miss handler.  Bit 27 is PAGE_USER, thus selecting the correct
30  * - PRESENT *must* be in the bottom two bits because swap PTEs
31  *   use the top 30 bits.  Because 40x doesn't support SMP anyway, M is
32  *   irrelevant so we borrow it for PAGE_PRESENT.  Bit 30
34  * - All other bits of the PTE are loaded into TLBLO without
44 #define	_PAGE_WRITETHRU	0x008	/* W: caching is write-through */
55 /* cache related flags non existing on 40x */