1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright (C) 2015-2016 Marvell International Ltd.
53 /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */
64 /* 40M1G25 mode init data */
67 	/*-----------------------------------------------------------*/
77 	0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00,	/* 40 */
144 	for (timeout = PLL_LOCK_TIMEOUT; timeout > 0; timeout--) {  in comphy_poll_reg()
146 			rval = readw(addr);	/* 16 bit */  in comphy_poll_reg()
148 			rval = readl(addr) ;	/* 32 bit */  in comphy_poll_reg()
177 	 * 2. Select 20 bit SERDES interface.  in comphy_pcie_power_up()
211 	if (get_ref_clk() == 40) {  in comphy_pcie_power_up()
212 		/* 40 MHz */  in comphy_pcie_power_up()
226 	 * 10. Check the Polarity invert bit  in comphy_pcie_power_up()
248 			      POLL_16B_REG);			/* 16bit */  in comphy_pcie_power_up()
286 	 * 1. Select 40-bit data width width  in comphy_sata_power_up()
293 	if (get_ref_clk() == 40) {  in comphy_sata_power_up()
294 		/* 40 MHz */  in comphy_sata_power_up()
307 	 * 4. Reset reserved bit (??)  in comphy_sata_power_up()
312 	 * 5. Set vendor-specific configuration (??)  in comphy_sata_power_up()
325 			      POLL_32B_REG);	/* 32bit */  in comphy_sata_power_up()
380 	/* set PRD_TXDEEMPH (3.5db de-emph) */  in comphy_usb3_power_up()
385 	 * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency  in comphy_usb3_power_up()
387 	 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db  in comphy_usb3_power_up()
388 	 *              together with bit 0 of COMPHY_REG_LANE_CFG0_ADDR  in comphy_usb3_power_up()
406 	/* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */  in comphy_usb3_power_up()
424 	if (get_ref_clk() == 40) {  in comphy_usb3_power_up()
425 		/* 40 MHz */  in comphy_usb3_power_up()
445 	 * 7. Set 20-bit data width  in comphy_usb3_power_up()
456 	 * 9. Check the Polarity invert bit  in comphy_usb3_power_up()
492 				      POLL_32B_REG);		/* 32bit */  in comphy_usb3_power_up()
497 				      POLL_16B_REG);		  /* 16bit */  in comphy_usb3_power_up()
546 	 * 0. Setup PLL. 40MHz clock uses defaults.  in comphy_usb2_power_up()
578 			      POLL_32B_REG);		/* 32bit */  in comphy_usb2_power_up()
586 			      POLL_32B_REG);		/* 32bit */  in comphy_usb2_power_up()
594 			      POLL_32B_REG);		/* 32bit */  in comphy_usb2_power_up()
602 			      POLL_32B_REG);		/* 32bit */  in comphy_usb2_power_up()
728 	 *    COMPHY bit rate  in comphy_sgmii_power_up()
766 	if (get_ref_clk() == 40) {  in comphy_sgmii_power_up()
787 	/* 10bit */  in comphy_sgmii_power_up()
805 	 *     group to get the related GEN table during real chip bring-up.  in comphy_sgmii_power_up()
808 	 *     40 MHz. For REF clock 25 MHz the default values stored in PHY  in comphy_sgmii_power_up()
811 	debug("Running C-DPI phy init %s mode\n",  in comphy_sgmii_power_up()
813 	if (get_ref_clk() == 40)  in comphy_sgmii_power_up()
828 	 * 18. Check the PHY Polarity invert bit  in comphy_sgmii_power_up()
853 			      POLL_32B_REG);			/* 32bit */  in comphy_sgmii_power_up()
875 			      POLL_32B_REG);			/* 32bit */  in comphy_sgmii_power_up()
892 	const void *blob = gd->fdt_blob;  in comphy_dedicated_phys_init()
903 				blob, -1, "marvell,armada3700-ehci");  in comphy_dedicated_phys_init()
906 				blob, -1, "marvell,armada3700-xhci");  in comphy_dedicated_phys_init()
925 	node = fdt_node_offset_by_compatible(blob, -1,  in comphy_dedicated_phys_init()
926 					     "marvell,armada-3700-ahci");  in comphy_dedicated_phys_init()
941 	node = fdt_node_offset_by_compatible(blob, -1,  in comphy_dedicated_phys_init()
942 					     "marvell,armada-8k-sdhci");  in comphy_dedicated_phys_init()
945 			blob, -1, "marvell,armada-3700-sdhci");  in comphy_dedicated_phys_init()
969 	u32 comphy_max_count = chip_cfg->comphy_lanes_count;  in comphy_a3700_init()
975 	chip_cfg->mux_data = a3700_comphy_mux_data;  in comphy_a3700_init()
982 		      comphy_map->type, comphy_map->invert);  in comphy_a3700_init()
984 		switch (comphy_map->type) {  in comphy_a3700_init()
990 			ret = comphy_pcie_power_up(comphy_map->speed,  in comphy_a3700_init()
991 						   comphy_map->invert);  in comphy_a3700_init()
997 						   comphy_map->type,  in comphy_a3700_init()
998 						   comphy_map->speed,  in comphy_a3700_init()
999 						   comphy_map->invert);  in comphy_a3700_init()
1004 			ret = comphy_sgmii_power_up(lane, comphy_map->speed,  in comphy_a3700_init()
1005 						    comphy_map->invert);  in comphy_a3700_init()
1015 			printf("PLL is not locked - Failed to initialize lane %d\n",  in comphy_a3700_init()