hw/riscv/riscv-iommu-bits.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * Copyright © 2022-2023 Rivos Inc.
4  * Copyright © 2023 FORTH-ICS/CARV
5  * Copyright © 2023 RISC-V IOMMU Task Group
7  * RISC-V IOMMU - Register Layout and Data Structures.
10  * https://github.com/riscv-non-isa/riscv-iommu
19 #define GENMASK_ULL(h, l) (((~0ULL) >> (63 - (h) + (l))) << (l))
23  * struct riscv_iommu_fq_record - Fault/Event Queue Record
37 #define RISCV_IOMMU_FQ_HDR_DID          GENMASK_ULL(63, 40)
40  * struct riscv_iommu_pq_record - PCIe Page Request record
52 #define RISCV_IOMMU_PREQ_HDR_DID        GENMASK_ULL(63, 40)
60 #define RISCV_IOMMU_QUEUE_ENABLE        BIT(0)
61 #define RISCV_IOMMU_QUEUE_INTR_ENABLE   BIT(1)
62 #define RISCV_IOMMU_QUEUE_MEM_FAULT     BIT(8)
63 #define RISCV_IOMMU_QUEUE_OVERFLOW      BIT(9)
64 #define RISCV_IOMMU_QUEUE_ACTIVE        BIT(16)
65 #define RISCV_IOMMU_QUEUE_BUSY          BIT(17)
89 #define RISCV_IOMMU_CAP_PD20            BIT_ULL(40)
93 #define RISCV_IOMMU_FCTL_BE             BIT(0)
94 #define RISCV_IOMMU_FCTL_WSI            BIT(1)
95 #define RISCV_IOMMU_FCTL_GXL            BIT(2)
97 /* 5.5 Device-directory-table pointer (64bits) */
150 #define RISCV_IOMMU_CQCSR_CMD_TO        BIT(9)
151 #define RISCV_IOMMU_CQCSR_CMD_ILL       BIT(10)
152 #define RISCV_IOMMU_CQCSR_FENCE_W_IP    BIT(11)
176 #define RISCV_IOMMU_IPSR_CIP            BIT(0)
177 #define RISCV_IOMMU_IPSR_FIP            BIT(1)
178 #define RISCV_IOMMU_IPSR_PIP            BIT(3)
196 #define RISCV_IOMMU_TR_REQ_CTL_DID      GENMASK_ULL(63, 40)
219 /* Struct riscv_iommu_dc - Device Context - section 2.1 */
245 /* Second-stage (aka G-stage) context fields */
261 /* First-stage context fields */
265 /* Generic I/O MMU command structure - check section 3.1 */
293 #define RISCV_IOMMU_CMD_IODIR_DID       GENMASK_ULL(63, 40)
302 #define RISCV_IOMMU_CMD_ATS_RID         GENMASK_ULL(55, 40)
384 #define RISCV_IOMMU_PREQ_HDR_DID        GENMASK_ULL(63, 40)
396  * struct riscv_iommu_msi_pte - MSI Page Table Entry