158f07778SDavid Daney /***********************license start***************
258f07778SDavid Daney * Author: Cavium Networks
358f07778SDavid Daney *
458f07778SDavid Daney * Contact: support@caviumnetworks.com
558f07778SDavid Daney * This file is part of the OCTEON SDK
658f07778SDavid Daney *
715f68479SSteven J. Hill * Copyright (c) 2003-2017 Cavium, Inc.
858f07778SDavid Daney *
958f07778SDavid Daney * This file is free software; you can redistribute it and/or modify
1058f07778SDavid Daney * it under the terms of the GNU General Public License, Version 2, as
1158f07778SDavid Daney * published by the Free Software Foundation.
1258f07778SDavid Daney *
1358f07778SDavid Daney * This file is distributed in the hope that it will be useful, but
1458f07778SDavid Daney * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
1558f07778SDavid Daney * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
1658f07778SDavid Daney * NONINFRINGEMENT. See the GNU General Public License for more
1758f07778SDavid Daney * details.
1858f07778SDavid Daney *
1958f07778SDavid Daney * You should have received a copy of the GNU General Public License
2058f07778SDavid Daney * along with this file; if not, write to the Free Software
2158f07778SDavid Daney * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
2258f07778SDavid Daney * or visit http://www.gnu.org/licenses/.
2358f07778SDavid Daney *
2458f07778SDavid Daney * This file may also be available under a different license from Cavium.
2558f07778SDavid Daney * Contact Cavium Networks for more information
2658f07778SDavid Daney ***********************license end**************************************/
2758f07778SDavid Daney
2858f07778SDavid Daney #ifndef __CVMX_H__
2958f07778SDavid Daney #define __CVMX_H__
3058f07778SDavid Daney
3158f07778SDavid Daney #include <linux/kernel.h>
3258f07778SDavid Daney #include <linux/string.h>
33edf188beSSteven J. Hill #include <linux/delay.h>
3458f07778SDavid Daney
3526afc5e3SDavid Daney enum cvmx_mips_space {
3626afc5e3SDavid Daney CVMX_MIPS_SPACE_XKSEG = 3LL,
3726afc5e3SDavid Daney CVMX_MIPS_SPACE_XKPHYS = 2LL,
3826afc5e3SDavid Daney CVMX_MIPS_SPACE_XSSEG = 1LL,
3926afc5e3SDavid Daney CVMX_MIPS_SPACE_XUSEG = 0LL
4026afc5e3SDavid Daney };
4126afc5e3SDavid Daney
4226afc5e3SDavid Daney /* These macros for use when using 32 bit pointers. */
4326afc5e3SDavid Daney #define CVMX_MIPS32_SPACE_KSEG0 1l
4426afc5e3SDavid Daney #define CVMX_ADD_SEG32(segment, add) \
4526afc5e3SDavid Daney (((int32_t)segment << 31) | (int32_t)(add))
4626afc5e3SDavid Daney
4726afc5e3SDavid Daney #define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
4826afc5e3SDavid Daney
4926afc5e3SDavid Daney /* These macros simplify the process of creating common IO addresses */
5026afc5e3SDavid Daney #define CVMX_ADD_SEG(segment, add) \
5126afc5e3SDavid Daney ((((uint64_t)segment) << 62) | (add))
5226afc5e3SDavid Daney #ifndef CVMX_ADD_IO_SEG
5326afc5e3SDavid Daney #define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
5426afc5e3SDavid Daney #endif
5526afc5e3SDavid Daney
56a1ce3928SDavid Howells #include <asm/octeon/cvmx-asm.h>
57a1ce3928SDavid Howells #include <asm/octeon/cvmx-packet.h>
58a1ce3928SDavid Howells #include <asm/octeon/cvmx-sysinfo.h>
5958f07778SDavid Daney
60a1ce3928SDavid Howells #include <asm/octeon/cvmx-ciu-defs.h>
61182a6d1cSDavid Daney #include <asm/octeon/cvmx-ciu3-defs.h>
62a1ce3928SDavid Howells #include <asm/octeon/cvmx-gpio-defs.h>
63a1ce3928SDavid Howells #include <asm/octeon/cvmx-iob-defs.h>
64a1ce3928SDavid Howells #include <asm/octeon/cvmx-ipd-defs.h>
65a1ce3928SDavid Howells #include <asm/octeon/cvmx-l2c-defs.h>
6681a67e52SSteven J. Hill #include <asm/octeon/cvmx-l2d-defs.h>
67a1ce3928SDavid Howells #include <asm/octeon/cvmx-l2t-defs.h>
68a1ce3928SDavid Howells #include <asm/octeon/cvmx-led-defs.h>
69a1ce3928SDavid Howells #include <asm/octeon/cvmx-mio-defs.h>
70a1ce3928SDavid Howells #include <asm/octeon/cvmx-pow-defs.h>
7158f07778SDavid Daney
72a1ce3928SDavid Howells #include <asm/octeon/cvmx-bootinfo.h>
73a1ce3928SDavid Howells #include <asm/octeon/cvmx-bootmem.h>
74a1ce3928SDavid Howells #include <asm/octeon/cvmx-l2c.h>
7558f07778SDavid Daney
7658f07778SDavid Daney #ifndef CVMX_ENABLE_DEBUG_PRINTS
7758f07778SDavid Daney #define CVMX_ENABLE_DEBUG_PRINTS 1
7858f07778SDavid Daney #endif
7958f07778SDavid Daney
8058f07778SDavid Daney #if CVMX_ENABLE_DEBUG_PRINTS
8158f07778SDavid Daney #define cvmx_dprintf printk
8258f07778SDavid Daney #else
8358f07778SDavid Daney #define cvmx_dprintf(...) {}
8458f07778SDavid Daney #endif
8558f07778SDavid Daney
8658f07778SDavid Daney #define CVMX_MAX_CORES (16)
8758f07778SDavid Daney #define CVMX_CACHE_LINE_SIZE (128) /* In bytes */
8858f07778SDavid Daney #define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1) /* In bytes */
8958f07778SDavid Daney #define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE)))
9058f07778SDavid Daney #define CAST64(v) ((long long)(long)(v))
9158f07778SDavid Daney #define CASTPTR(type, v) ((type *)(long)(v))
9258f07778SDavid Daney
9358f07778SDavid Daney /*
9458f07778SDavid Daney * Returns processor ID, different Linux and simple exec versions
9558f07778SDavid Daney * provided in the cvmx-app-init*.c files.
9658f07778SDavid Daney */
9758f07778SDavid Daney static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
cvmx_get_proc_id(void)9858f07778SDavid Daney static inline uint32_t cvmx_get_proc_id(void)
9958f07778SDavid Daney {
10058f07778SDavid Daney uint32_t id;
10158f07778SDavid Daney asm("mfc0 %0, $15,0" : "=r"(id));
10258f07778SDavid Daney return id;
10358f07778SDavid Daney }
10458f07778SDavid Daney
10558f07778SDavid Daney /* turn the variable name into a string */
10658f07778SDavid Daney #define CVMX_TMP_STR(x) CVMX_TMP_STR2(x)
10758f07778SDavid Daney #define CVMX_TMP_STR2(x) #x
10858f07778SDavid Daney
10958f07778SDavid Daney /**
11058f07778SDavid Daney * Builds a bit mask given the required size in bits.
11158f07778SDavid Daney *
11258f07778SDavid Daney * @bits: Number of bits in the mask
11358f07778SDavid Daney * Returns The mask
cvmx_build_mask(uint64_t bits)11458f07778SDavid Daney */ static inline uint64_t cvmx_build_mask(uint64_t bits)
11558f07778SDavid Daney {
11658f07778SDavid Daney return ~((~0x0ull) << bits);
11758f07778SDavid Daney }
11858f07778SDavid Daney
11958f07778SDavid Daney /**
12058f07778SDavid Daney * Builds a memory address for I/O based on the Major and Sub DID.
12158f07778SDavid Daney *
12258f07778SDavid Daney * @major_did: 5 bit major did
12358f07778SDavid Daney * @sub_did: 3 bit sub did
12458f07778SDavid Daney * Returns I/O base address
12558f07778SDavid Daney */
cvmx_build_io_address(uint64_t major_did,uint64_t sub_did)12658f07778SDavid Daney static inline uint64_t cvmx_build_io_address(uint64_t major_did,
12758f07778SDavid Daney uint64_t sub_did)
12858f07778SDavid Daney {
12958f07778SDavid Daney return (0x1ull << 48) | (major_did << 43) | (sub_did << 40);
13058f07778SDavid Daney }
13158f07778SDavid Daney
13258f07778SDavid Daney /**
13358f07778SDavid Daney * Perform mask and shift to place the supplied value into
13458f07778SDavid Daney * the supplied bit rage.
13558f07778SDavid Daney *
13658f07778SDavid Daney * Example: cvmx_build_bits(39,24,value)
13758f07778SDavid Daney * <pre>
13858f07778SDavid Daney * 6 5 4 3 3 2 1
13958f07778SDavid Daney * 3 5 7 9 1 3 5 7 0
14058f07778SDavid Daney * +-------+-------+-------+-------+-------+-------+-------+------+
14158f07778SDavid Daney * 000000000000000000000000___________value000000000000000000000000
14258f07778SDavid Daney * </pre>
14358f07778SDavid Daney *
14458f07778SDavid Daney * @high_bit: Highest bit value can occupy (inclusive) 0-63
14558f07778SDavid Daney * @low_bit: Lowest bit value can occupy inclusive 0-high_bit
14658f07778SDavid Daney * @value: Value to use
14758f07778SDavid Daney * Returns Value masked and shifted
14858f07778SDavid Daney */
cvmx_build_bits(uint64_t high_bit,uint64_t low_bit,uint64_t value)14958f07778SDavid Daney static inline uint64_t cvmx_build_bits(uint64_t high_bit,
15058f07778SDavid Daney uint64_t low_bit, uint64_t value)
15158f07778SDavid Daney {
15258f07778SDavid Daney return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit;
15358f07778SDavid Daney }
15458f07778SDavid Daney
15558f07778SDavid Daney /**
15625985edcSLucas De Marchi * Convert a memory pointer (void*) into a hardware compatible
157*3cbb8d0dSGeert Uytterhoeven * memory address (phys_addr_t). Octeon hardware widgets don't
15858f07778SDavid Daney * understand logical addresses.
15958f07778SDavid Daney *
16058f07778SDavid Daney * @ptr: C style memory pointer
16158f07778SDavid Daney * Returns Hardware physical address
16258f07778SDavid Daney */
cvmx_ptr_to_phys(void * ptr)163*3cbb8d0dSGeert Uytterhoeven static inline phys_addr_t cvmx_ptr_to_phys(void *ptr)
16458f07778SDavid Daney {
16558f07778SDavid Daney if (sizeof(void *) == 8) {
16658f07778SDavid Daney /*
16758f07778SDavid Daney * We're running in 64 bit mode. Normally this means
16858f07778SDavid Daney * that we can use 40 bits of address space (the
16958f07778SDavid Daney * hardware limit). Unfortunately there is one case
17058f07778SDavid Daney * were we need to limit this to 30 bits, sign
17158f07778SDavid Daney * extended 32 bit. Although these are 64 bits wide,
17258f07778SDavid Daney * only 30 bits can be used.
17358f07778SDavid Daney */
17458f07778SDavid Daney if ((CAST64(ptr) >> 62) == 3)
17558f07778SDavid Daney return CAST64(ptr) & cvmx_build_mask(30);
17658f07778SDavid Daney else
17758f07778SDavid Daney return CAST64(ptr) & cvmx_build_mask(40);
17858f07778SDavid Daney } else {
17958f07778SDavid Daney return (long)(ptr) & 0x1fffffff;
18058f07778SDavid Daney }
18158f07778SDavid Daney }
18258f07778SDavid Daney
18358f07778SDavid Daney /**
18458f07778SDavid Daney * Convert a hardware physical address (uint64_t) into a
18558f07778SDavid Daney * memory pointer (void *).
18658f07778SDavid Daney *
18758f07778SDavid Daney * @physical_address:
18858f07778SDavid Daney * Hardware physical address to memory
18958f07778SDavid Daney * Returns Pointer to memory
19058f07778SDavid Daney */
cvmx_phys_to_ptr(uint64_t physical_address)19158f07778SDavid Daney static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
19258f07778SDavid Daney {
19358f07778SDavid Daney if (sizeof(void *) == 8) {
19492a76f6dSAdam Buchbinder /* Just set the top bit, avoiding any TLB ugliness */
19558f07778SDavid Daney return CASTPTR(void,
19658f07778SDavid Daney CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
19758f07778SDavid Daney physical_address));
19858f07778SDavid Daney } else {
19958f07778SDavid Daney return CASTPTR(void,
20058f07778SDavid Daney CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0,
20158f07778SDavid Daney physical_address));
20258f07778SDavid Daney }
20358f07778SDavid Daney }
20458f07778SDavid Daney
20558f07778SDavid Daney /* The following #if controls the definition of the macro
20658f07778SDavid Daney CVMX_BUILD_WRITE64. This macro is used to build a store operation to
20758f07778SDavid Daney a full 64bit address. With a 64bit ABI, this can be done with a simple
20858f07778SDavid Daney pointer access. 32bit ABIs require more complicated assembly */
20958f07778SDavid Daney
21058f07778SDavid Daney /* We have a full 64bit ABI. Writing to a 64bit address can be done with
21158f07778SDavid Daney a simple volatile pointer */
21258f07778SDavid Daney #define CVMX_BUILD_WRITE64(TYPE, ST) \
21358f07778SDavid Daney static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \
21458f07778SDavid Daney { \
21558f07778SDavid Daney *CASTPTR(volatile TYPE##_t, addr) = val; \
21658f07778SDavid Daney }
21758f07778SDavid Daney
21858f07778SDavid Daney
21958f07778SDavid Daney /* The following #if controls the definition of the macro
22058f07778SDavid Daney CVMX_BUILD_READ64. This macro is used to build a load operation from
22158f07778SDavid Daney a full 64bit address. With a 64bit ABI, this can be done with a simple
22258f07778SDavid Daney pointer access. 32bit ABIs require more complicated assembly */
22358f07778SDavid Daney
22458f07778SDavid Daney /* We have a full 64bit ABI. Writing to a 64bit address can be done with
22558f07778SDavid Daney a simple volatile pointer */
22658f07778SDavid Daney #define CVMX_BUILD_READ64(TYPE, LT) \
22758f07778SDavid Daney static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr) \
22858f07778SDavid Daney { \
22958f07778SDavid Daney return *CASTPTR(volatile TYPE##_t, addr); \
23058f07778SDavid Daney }
23158f07778SDavid Daney
23258f07778SDavid Daney
23358f07778SDavid Daney /* The following defines 8 functions for writing to a 64bit address. Each
23458f07778SDavid Daney takes two arguments, the address and the value to write.
23558f07778SDavid Daney cvmx_write64_int64 cvmx_write64_uint64
23658f07778SDavid Daney cvmx_write64_int32 cvmx_write64_uint32
23758f07778SDavid Daney cvmx_write64_int16 cvmx_write64_uint16
23858f07778SDavid Daney cvmx_write64_int8 cvmx_write64_uint8 */
23958f07778SDavid Daney CVMX_BUILD_WRITE64(int64, "sd");
24058f07778SDavid Daney CVMX_BUILD_WRITE64(int32, "sw");
24158f07778SDavid Daney CVMX_BUILD_WRITE64(int16, "sh");
24258f07778SDavid Daney CVMX_BUILD_WRITE64(int8, "sb");
24358f07778SDavid Daney CVMX_BUILD_WRITE64(uint64, "sd");
24458f07778SDavid Daney CVMX_BUILD_WRITE64(uint32, "sw");
24558f07778SDavid Daney CVMX_BUILD_WRITE64(uint16, "sh");
24658f07778SDavid Daney CVMX_BUILD_WRITE64(uint8, "sb");
24758f07778SDavid Daney #define cvmx_write64 cvmx_write64_uint64
24858f07778SDavid Daney
24958f07778SDavid Daney /* The following defines 8 functions for reading from a 64bit address. Each
25058f07778SDavid Daney takes the address as the only argument
25158f07778SDavid Daney cvmx_read64_int64 cvmx_read64_uint64
25258f07778SDavid Daney cvmx_read64_int32 cvmx_read64_uint32
25358f07778SDavid Daney cvmx_read64_int16 cvmx_read64_uint16
25458f07778SDavid Daney cvmx_read64_int8 cvmx_read64_uint8 */
25558f07778SDavid Daney CVMX_BUILD_READ64(int64, "ld");
25658f07778SDavid Daney CVMX_BUILD_READ64(int32, "lw");
25758f07778SDavid Daney CVMX_BUILD_READ64(int16, "lh");
25858f07778SDavid Daney CVMX_BUILD_READ64(int8, "lb");
25958f07778SDavid Daney CVMX_BUILD_READ64(uint64, "ld");
26058f07778SDavid Daney CVMX_BUILD_READ64(uint32, "lw");
26158f07778SDavid Daney CVMX_BUILD_READ64(uint16, "lhu");
26258f07778SDavid Daney CVMX_BUILD_READ64(uint8, "lbu");
26358f07778SDavid Daney #define cvmx_read64 cvmx_read64_uint64
26458f07778SDavid Daney
26558f07778SDavid Daney
cvmx_write_csr(uint64_t csr_addr,uint64_t val)26658f07778SDavid Daney static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
26758f07778SDavid Daney {
26858f07778SDavid Daney cvmx_write64(csr_addr, val);
26958f07778SDavid Daney
27058f07778SDavid Daney /*
27158f07778SDavid Daney * Perform an immediate read after every write to an RSL
27258f07778SDavid Daney * register to force the write to complete. It doesn't matter
27358f07778SDavid Daney * what RSL read we do, so we choose CVMX_MIO_BOOT_BIST_STAT
27458f07778SDavid Daney * because it is fast and harmless.
27558f07778SDavid Daney */
27626084411SDavid Daney if (((csr_addr >> 40) & 0x7ffff) == (0x118))
27758f07778SDavid Daney cvmx_read64(CVMX_MIO_BOOT_BIST_STAT);
27858f07778SDavid Daney }
27958f07778SDavid Daney
cvmx_writeq_csr(void __iomem * csr_addr,uint64_t val)280a2127e40SAleksey Makarov static inline void cvmx_writeq_csr(void __iomem *csr_addr, uint64_t val)
281a2127e40SAleksey Makarov {
282a2127e40SAleksey Makarov cvmx_write_csr((__force uint64_t)csr_addr, val);
283a2127e40SAleksey Makarov }
284a2127e40SAleksey Makarov
cvmx_write_io(uint64_t io_addr,uint64_t val)28558f07778SDavid Daney static inline void cvmx_write_io(uint64_t io_addr, uint64_t val)
28658f07778SDavid Daney {
28758f07778SDavid Daney cvmx_write64(io_addr, val);
28858f07778SDavid Daney
28958f07778SDavid Daney }
29058f07778SDavid Daney
cvmx_read_csr(uint64_t csr_addr)29158f07778SDavid Daney static inline uint64_t cvmx_read_csr(uint64_t csr_addr)
29258f07778SDavid Daney {
29358f07778SDavid Daney uint64_t val = cvmx_read64(csr_addr);
29458f07778SDavid Daney return val;
29558f07778SDavid Daney }
29658f07778SDavid Daney
cvmx_readq_csr(void __iomem * csr_addr)297a2127e40SAleksey Makarov static inline uint64_t cvmx_readq_csr(void __iomem *csr_addr)
298a2127e40SAleksey Makarov {
299a2127e40SAleksey Makarov return cvmx_read_csr((__force uint64_t) csr_addr);
300a2127e40SAleksey Makarov }
30158f07778SDavid Daney
cvmx_send_single(uint64_t data)30258f07778SDavid Daney static inline void cvmx_send_single(uint64_t data)
30358f07778SDavid Daney {
30458f07778SDavid Daney const uint64_t CVMX_IOBDMA_SENDSINGLE = 0xffffffffffffa200ull;
30558f07778SDavid Daney cvmx_write64(CVMX_IOBDMA_SENDSINGLE, data);
30658f07778SDavid Daney }
30758f07778SDavid Daney
cvmx_read_csr_async(uint64_t scraddr,uint64_t csr_addr)30858f07778SDavid Daney static inline void cvmx_read_csr_async(uint64_t scraddr, uint64_t csr_addr)
30958f07778SDavid Daney {
31058f07778SDavid Daney union {
31158f07778SDavid Daney uint64_t u64;
31258f07778SDavid Daney struct {
31358f07778SDavid Daney uint64_t scraddr:8;
31458f07778SDavid Daney uint64_t len:8;
31558f07778SDavid Daney uint64_t addr:48;
31658f07778SDavid Daney } s;
31758f07778SDavid Daney } addr;
31858f07778SDavid Daney addr.u64 = csr_addr;
31958f07778SDavid Daney addr.s.scraddr = scraddr >> 3;
32058f07778SDavid Daney addr.s.len = 1;
32158f07778SDavid Daney cvmx_send_single(addr.u64);
32258f07778SDavid Daney }
32358f07778SDavid Daney
32458f07778SDavid Daney /* Return true if Octeon is CN38XX pass 1 */
cvmx_octeon_is_pass1(void)32558f07778SDavid Daney static inline int cvmx_octeon_is_pass1(void)
32658f07778SDavid Daney {
32758f07778SDavid Daney #if OCTEON_IS_COMMON_BINARY()
32858f07778SDavid Daney return 0; /* Pass 1 isn't supported for common binaries */
32958f07778SDavid Daney #else
33058f07778SDavid Daney /* Now that we know we're built for a specific model, only check CN38XX */
33158f07778SDavid Daney #if OCTEON_IS_MODEL(OCTEON_CN38XX)
33258f07778SDavid Daney return cvmx_get_proc_id() == OCTEON_CN38XX_PASS1;
33358f07778SDavid Daney #else
33458f07778SDavid Daney return 0; /* Built for non CN38XX chip, we're not CN38XX pass1 */
33558f07778SDavid Daney #endif
33658f07778SDavid Daney #endif
33758f07778SDavid Daney }
33858f07778SDavid Daney
cvmx_get_core_num(void)33958f07778SDavid Daney static inline unsigned int cvmx_get_core_num(void)
34058f07778SDavid Daney {
34158f07778SDavid Daney unsigned int core_num;
34258f07778SDavid Daney CVMX_RDHWRNV(core_num, 0);
34358f07778SDavid Daney return core_num;
34458f07778SDavid Daney }
34558f07778SDavid Daney
346182a6d1cSDavid Daney /* Maximum # of bits to define core in node */
347182a6d1cSDavid Daney #define CVMX_NODE_NO_SHIFT 7
348182a6d1cSDavid Daney #define CVMX_NODE_MASK 0x3
cvmx_get_node_num(void)349182a6d1cSDavid Daney static inline unsigned int cvmx_get_node_num(void)
350182a6d1cSDavid Daney {
351182a6d1cSDavid Daney unsigned int core_num = cvmx_get_core_num();
352182a6d1cSDavid Daney
353182a6d1cSDavid Daney return (core_num >> CVMX_NODE_NO_SHIFT) & CVMX_NODE_MASK;
354182a6d1cSDavid Daney }
355182a6d1cSDavid Daney
cvmx_get_local_core_num(void)356182a6d1cSDavid Daney static inline unsigned int cvmx_get_local_core_num(void)
357182a6d1cSDavid Daney {
358182a6d1cSDavid Daney return cvmx_get_core_num() & ((1 << CVMX_NODE_NO_SHIFT) - 1);
359182a6d1cSDavid Daney }
360182a6d1cSDavid Daney
3613c425df7SSteven J. Hill #define CVMX_NODE_BITS (2) /* Number of bits to define a node */
3623c425df7SSteven J. Hill #define CVMX_MAX_NODES (1 << CVMX_NODE_BITS)
3633c425df7SSteven J. Hill #define CVMX_NODE_IO_SHIFT (36)
3643c425df7SSteven J. Hill #define CVMX_NODE_MEM_SHIFT (40)
3653c425df7SSteven J. Hill #define CVMX_NODE_IO_MASK ((uint64_t)CVMX_NODE_MASK << CVMX_NODE_IO_SHIFT)
3663c425df7SSteven J. Hill
cvmx_write_csr_node(uint64_t node,uint64_t csr_addr,uint64_t val)3673c425df7SSteven J. Hill static inline void cvmx_write_csr_node(uint64_t node, uint64_t csr_addr,
3683c425df7SSteven J. Hill uint64_t val)
3693c425df7SSteven J. Hill {
3703c425df7SSteven J. Hill uint64_t composite_csr_addr, node_addr;
3713c425df7SSteven J. Hill
3723c425df7SSteven J. Hill node_addr = (node & CVMX_NODE_MASK) << CVMX_NODE_IO_SHIFT;
3733c425df7SSteven J. Hill composite_csr_addr = (csr_addr & ~CVMX_NODE_IO_MASK) | node_addr;
3743c425df7SSteven J. Hill
3753c425df7SSteven J. Hill cvmx_write64_uint64(composite_csr_addr, val);
3763c425df7SSteven J. Hill if (((csr_addr >> 40) & 0x7ffff) == (0x118))
3773c425df7SSteven J. Hill cvmx_read64_uint64(CVMX_MIO_BOOT_BIST_STAT | node_addr);
3783c425df7SSteven J. Hill }
3793c425df7SSteven J. Hill
cvmx_read_csr_node(uint64_t node,uint64_t csr_addr)3803c425df7SSteven J. Hill static inline uint64_t cvmx_read_csr_node(uint64_t node, uint64_t csr_addr)
3813c425df7SSteven J. Hill {
3823c425df7SSteven J. Hill uint64_t node_addr;
3833c425df7SSteven J. Hill
3843c425df7SSteven J. Hill node_addr = (csr_addr & ~CVMX_NODE_IO_MASK) |
3853c425df7SSteven J. Hill (node & CVMX_NODE_MASK) << CVMX_NODE_IO_SHIFT;
3863c425df7SSteven J. Hill return cvmx_read_csr(node_addr);
3873c425df7SSteven J. Hill }
3883c425df7SSteven J. Hill
38958f07778SDavid Daney /**
39058f07778SDavid Daney * Returns the number of bits set in the provided value.
39158f07778SDavid Daney * Simple wrapper for POP instruction.
39258f07778SDavid Daney *
39358f07778SDavid Daney * @val: 32 bit value to count set bits in
39458f07778SDavid Daney *
39558f07778SDavid Daney * Returns Number of bits set
39658f07778SDavid Daney */
cvmx_pop(uint32_t val)39758f07778SDavid Daney static inline uint32_t cvmx_pop(uint32_t val)
39858f07778SDavid Daney {
39958f07778SDavid Daney uint32_t pop;
40058f07778SDavid Daney CVMX_POP(pop, val);
40158f07778SDavid Daney return pop;
40258f07778SDavid Daney }
40358f07778SDavid Daney
40458f07778SDavid Daney /**
40558f07778SDavid Daney * Returns the number of bits set in the provided value.
40658f07778SDavid Daney * Simple wrapper for DPOP instruction.
40758f07778SDavid Daney *
40858f07778SDavid Daney * @val: 64 bit value to count set bits in
40958f07778SDavid Daney *
41058f07778SDavid Daney * Returns Number of bits set
41158f07778SDavid Daney */
cvmx_dpop(uint64_t val)41258f07778SDavid Daney static inline int cvmx_dpop(uint64_t val)
41358f07778SDavid Daney {
41458f07778SDavid Daney int pop;
41558f07778SDavid Daney CVMX_DPOP(pop, val);
41658f07778SDavid Daney return pop;
41758f07778SDavid Daney }
41858f07778SDavid Daney
41958f07778SDavid Daney /**
42058f07778SDavid Daney * Provide current cycle counter as a return value
42158f07778SDavid Daney *
42258f07778SDavid Daney * Returns current cycle counter
42358f07778SDavid Daney */
42458f07778SDavid Daney
cvmx_get_cycle(void)42558f07778SDavid Daney static inline uint64_t cvmx_get_cycle(void)
42658f07778SDavid Daney {
42758f07778SDavid Daney uint64_t cycle;
42858f07778SDavid Daney CVMX_RDHWR(cycle, 31);
42958f07778SDavid Daney return cycle;
43058f07778SDavid Daney }
43158f07778SDavid Daney
43258f07778SDavid Daney /**
43358f07778SDavid Daney * Reads a chip global cycle counter. This counts CPU cycles since
43458f07778SDavid Daney * chip reset. The counter is 64 bit.
43558f07778SDavid Daney * This register does not exist on CN38XX pass 1 silicion
43658f07778SDavid Daney *
43758f07778SDavid Daney * Returns Global chip cycle count since chip reset.
43858f07778SDavid Daney */
cvmx_get_cycle_global(void)43958f07778SDavid Daney static inline uint64_t cvmx_get_cycle_global(void)
44058f07778SDavid Daney {
44158f07778SDavid Daney if (cvmx_octeon_is_pass1())
44258f07778SDavid Daney return 0;
44358f07778SDavid Daney else
44458f07778SDavid Daney return cvmx_read64(CVMX_IPD_CLK_COUNT);
44558f07778SDavid Daney }
44658f07778SDavid Daney
44758f07778SDavid Daney /**
44858f07778SDavid Daney * This macro spins on a field waiting for it to reach a value. It
44958f07778SDavid Daney * is common in code to need to wait for a specific field in a CSR
45058f07778SDavid Daney * to match a specific value. Conceptually this macro expands to:
45158f07778SDavid Daney *
45258f07778SDavid Daney * 1) read csr at "address" with a csr typedef of "type"
45358f07778SDavid Daney * 2) Check if ("type".s."field" "op" "value")
45458f07778SDavid Daney * 3) If #2 isn't true loop to #1 unless too much time has passed.
45558f07778SDavid Daney */
45658f07778SDavid Daney #define CVMX_WAIT_FOR_FIELD64(address, type, field, op, value, timeout_usec)\
45758f07778SDavid Daney ( \
45858f07778SDavid Daney { \
45958f07778SDavid Daney int result; \
46058f07778SDavid Daney do { \
46158f07778SDavid Daney uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \
46258f07778SDavid Daney cvmx_sysinfo_get()->cpu_clock_hz / 1000000; \
46358f07778SDavid Daney type c; \
46458f07778SDavid Daney while (1) { \
46558f07778SDavid Daney c.u64 = cvmx_read_csr(address); \
46658f07778SDavid Daney if ((c.s.field) op(value)) { \
46758f07778SDavid Daney result = 0; \
46858f07778SDavid Daney break; \
46958f07778SDavid Daney } else if (cvmx_get_cycle() > done) { \
47058f07778SDavid Daney result = -1; \
47158f07778SDavid Daney break; \
47258f07778SDavid Daney } else \
473edf188beSSteven J. Hill __delay(100); \
47458f07778SDavid Daney } \
47558f07778SDavid Daney } while (0); \
47658f07778SDavid Daney result; \
47758f07778SDavid Daney })
47858f07778SDavid Daney
47958f07778SDavid Daney /***************************************************************************/
48058f07778SDavid Daney
48158f07778SDavid Daney /* Return the number of cores available in the chip */
cvmx_octeon_num_cores(void)48258f07778SDavid Daney static inline uint32_t cvmx_octeon_num_cores(void)
48358f07778SDavid Daney {
484182a6d1cSDavid Daney u64 ciu_fuse_reg;
485182a6d1cSDavid Daney u64 ciu_fuse;
486182a6d1cSDavid Daney
487182a6d1cSDavid Daney if (OCTEON_IS_OCTEON3() && !OCTEON_IS_MODEL(OCTEON_CN70XX))
488182a6d1cSDavid Daney ciu_fuse_reg = CVMX_CIU3_FUSE;
489182a6d1cSDavid Daney else
490182a6d1cSDavid Daney ciu_fuse_reg = CVMX_CIU_FUSE;
491182a6d1cSDavid Daney ciu_fuse = cvmx_read_csr(ciu_fuse_reg);
492182a6d1cSDavid Daney return cvmx_dpop(ciu_fuse);
49358f07778SDavid Daney }
49458f07778SDavid Daney
49558f07778SDavid Daney #endif /* __CVMX_H__ */
496