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/openbmc/linux/drivers/phy/marvell/
H A Dphy-mvebu-cp110-comphy.c1 // SPDX-License-Identifier: GPL-2.0
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
8 #include <linux/arm-smccc.h>
20 /* Relative to priv->base */
31 #define MVEBU_COMPHY_SERDES_CFG1_RX_INIT BIT(4)
35 #define MVEBU_COMPHY_SERDES_CFG2_DFE_EN BIT(4)
39 #define MVEBU_COMPHY_SERDES_STATUS0_RX_INIT BIT(4)
63 #define MVEBU_COMPHY_GEN1_S2_TX_EMPH_EN BIT(4)
108 /* Relative to priv->regmap */
129 * A lane is described by the following bitfields:
[all …]
H A Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
40 * When accessing common PHY lane registers directly, we need to shift by 1,
41 * since the registers are 16-bit.
55 #define REF_FREF_SEL_MASK GENMASK(4, 0)
77 #define PLL_READY_TX_BIT BIT(4)
110 #define CLK100M_125M_EN BIT(4)
130 #define PRD_TXSWING_MASK BIT(4)
137 #define GEN2_TX_DATA_DLY_MASK GENMASK(4, 3)
152 #define MODE_REFDIV_MASK GENMASK(5, 4)
[all …]
H A Dphy-armada38x-comphy.c1 // SPDX-License-Identifier: GPL-2.0
47 struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; member
52 { 4, 5, 0 },
53 { 0, 4, 0 },
54 { 0, 0, 4 },
59 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) in a38x_set_conf() argument
61 struct a38x_comphy *priv = lane->priv; in a38x_set_conf()
64 if (priv->conf) { in a38x_set_conf()
65 conf = readl_relaxed(priv->conf); in a38x_set_conf()
67 conf |= BIT(lane->port); in a38x_set_conf()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_training_fixed_vs_pe_retimer.c42 link->ctx->logger
52 uint8_t lane; in dp_fixed_vs_pe_read_lane_adjust() local
54 /* W/A to read lane settings requested by DPRX */ in dp_fixed_vs_pe_read_lane_adjust()
55 link_configure_fixed_vs_pe_retimer(link->ddc, in dp_fixed_vs_pe_read_lane_adjust()
58 link_query_fixed_vs_pe_retimer(link->ddc, &dprx_vs, 1); in dp_fixed_vs_pe_read_lane_adjust()
60 link_configure_fixed_vs_pe_retimer(link->ddc, in dp_fixed_vs_pe_read_lane_adjust()
63 link_query_fixed_vs_pe_retimer(link->ddc, &dprx_pe, 1); in dp_fixed_vs_pe_read_lane_adjust()
65 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_fixed_vs_pe_read_lane_adjust()
66 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_SET = (dprx_vs >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust()
67 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_SET = (dprx_pe >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust()
[all …]
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/axp/
H A Dhigh_speed_env_spec.h1 /* SPDX-License-Identifier: GPL-2.0 */
52 MV_PEX_UNIT_CFG pex_mode[4];
55 * Bus speed - one bit per SERDES line:
68 {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 0 */ \
69 {0, 1, -1 , -1, -1, -1, -1, -1, 2}, /* Lane 1 */ \
70 {0, 1, -1 , 2, -1, -1, -1, -1, 3}, /* Lane 2 */ \
71 {0, 1, -1 , -1, 2, -1, -1, 3, -1}, /* Lane 3 */ \
72 {0, 1, 2 , -1, -1, 3, -1, -1, 4}, /* Lane 4 */ \
73 {0, 1, 2 , -1, 3, -1, -1, 4, -1}, /* Lane 5 */ \
74 {0, 1, 2 , 4, -1, 3, -1, -1, -1}, /* Lane 6 */ \
[all …]
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_cx0_phy_regs.h1 /* SPDX-License-Identifier: MIT
15 #define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ argument
19 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4)
30 #define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ argument
34 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8)
74 #define XELPDP_TCSS_POWER_STATE REG_BIT(4)
82 _XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 4)
84 #define XELPDP_LANE_PIPE_RESET(lane) _PICK(lane, REG_BIT(31), REG_BIT(30)) argument
85 #define XELPDP_LANE_PHY_CURRENT_STATUS(lane) _PICK(lane, REG_BIT(29), REG_BIT(28)) argument
86 #define XELPDP_LANE_POWERDOWN_UPDATE(lane) _PICK(lane, REG_BIT(25), REG_BIT(24)) argument
[all …]
/openbmc/linux/drivers/phy/tegra/
H A Dxusb-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
31 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_SHIFT(x) ((x) * 4)
39 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 4) + 3))
40 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_SHIFT(x) ((x) * 4)
41 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(x) (0x7 << ((x) * 4))
42 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(x, v) (((v) & 0x7) << ((x) * 4))
49 #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_VCORE_DOWN(x) (1 << (18 + (x) * 4))
51 (1 << (17 + (x) * 4))
52 #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_CLAMP_EN(x) (1 << (16 + (x) * 4))
62 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
[all …]
H A Dxusb-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
27 ((x) ? (11 + ((x) - 1) * 6) : 0)
44 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(x) (0x0 << ((x) * 4))
45 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(x) (0x1 << ((x) * 4))
46 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(x) (0x2 << ((x) * 4))
47 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(x) (0x3 << ((x) * 4))
48 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(x) (0x3 << ((x) * 4))
51 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 5) + 4))
144 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 (1 << 4)
[all …]
H A Dxusb-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
42 #define PORTX_CAP_SHIFT(x) ((x) * 4)
67 #define PORTX_SPEED_SUPPORT_SHIFT(x) ((x) * 4)
101 #define HSIC_PD_RX_DATA0 BIT(4)
123 #define UHSIC_LINE_DEB_CNT(x) (((x) & 0xf) << 4)
126 #define XUSB_AO_UTMIP_TRIGGERS(x) (0x40 + (x) * 4)
131 #define XUSB_AO_UHSIC_TRIGGERS(x) (0x60 + (x) * 4)
134 #define HSIC_CAP_CFG BIT(4)
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dfsl_corenet_serdes.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
19 * The work-arounds for erratum SERDES8 and SERDES-A001 are linked together.
61 unsigned int lpd; /* RCW lane powerdown bit */
68 { 4, 156, FSL_SRDS_BANK_1 },
95 int serdes_get_lane_idx(int lane) in serdes_get_lane_idx() argument
97 return lanes[lane].idx; in serdes_get_lane_idx()
100 int serdes_get_bank_by_lane(int lane) in serdes_get_bank_by_lane() argument
102 return lanes[lane].bank; in serdes_get_bank_by_lane()
105 int serdes_lane_enabled(int lane) in serdes_lane_enabled() argument
[all …]
/openbmc/u-boot/board/highbank/
H A Dahci.c1 // SPDX-License-Identifier: GPL-2.0+
81 static void cphy_spread_spectrum_override(u8 phy, u8 lane, u32 val) in cphy_spread_spectrum_override() argument
84 tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE); in cphy_spread_spectrum_override()
86 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
89 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
93 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
96 static void cphy_tx_attenuation_override(u8 phy, u8 lane) in cphy_tx_attenuation_override() argument
102 shift = ((phy == 5) ? 4 : lane) * 4; in cphy_tx_attenuation_override()
109 tmp = combo_phy_read(phy, CPHY_TX_INPUT_STS + lane * SPHY_LANE); in cphy_tx_attenuation_override()
111 combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_tx_attenuation_override()
[all …]
/openbmc/linux/sound/soc/tegra/
H A Dtegra186_asrc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // tegra186_asrc.c - Tegra186 ASRC driver
32 (((id) + 1) << 4) }, \
49 ASRC_STREAM_REG_DEFAULTS(4),
74 regmap_write(asrc->regmap, in tegra186_asrc_lock_stream()
84 regcache_cache_only(asrc->regmap, true); in tegra186_asrc_runtime_suspend()
85 regcache_mark_dirty(asrc->regmap); in tegra186_asrc_runtime_suspend()
95 regcache_cache_only(asrc->regmap, false); in tegra186_asrc_runtime_resume()
102 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR, in tegra186_asrc_runtime_resume()
104 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_ENB, in tegra186_asrc_runtime_resume()
[all …]
/openbmc/u-boot/board/freescale/ls1043aqds/
H A Deth.c1 // SPDX-License-Identifier: GPL-2.0+
26 #define EMI1_SLOT3 4
42 /* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
43 static u8 lane_to_slot[] = {1, 2, 3, 4};
85 brdcfg4 = QIXIS_READ(brdcfg[4]); in ls1043aqds_mux_mdio()
88 QIXIS_WRITE(brdcfg[4], brdcfg4); in ls1043aqds_mux_mdio()
95 struct ls1043aqds_mdio *priv = bus->priv; in ls1043aqds_mdio_read()
97 ls1043aqds_mux_mdio(priv->muxval); in ls1043aqds_mdio_read()
99 return priv->realbus->read(priv->realbus, addr, devad, regnum); in ls1043aqds_mdio_read()
105 struct ls1043aqds_mdio *priv = bus->priv; in ls1043aqds_mdio_write()
[all …]
/openbmc/u-boot/drivers/ram/stm32mp1/
H A Dstm32mp1_ddr_regs.h1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
13 u8 reserved008[0x10 - 0x8];
20 u8 reserved028[0x30 - 0x28];
24 u8 reserved03c[0x50 - 0x3C];
31 u8 reserved068[0xc0 - 0x68];
40 u32 init4; /* 0xe0 SDRAM Initialization 4*/
45 u8 reserved0f4[0x100 - 0xf4];
50 u32 dramtmg4; /* 0x110 SDRAM Timing 4*/
55 u8 reserved124[0x138 - 0x124];
[all …]
/openbmc/u-boot/board/freescale/t1040qds/
H A Deth.c1 // SPDX-License-Identifier: GPL-2.0+
7 * The RGMII PHYs are provided by the two on-board PHY connected to
8 * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board
9 * PHY or by the standard four-port SGMII riser card (VSC).
28 /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks.
29 * Bank 1 -> Lanes A, B, C, D
30 * Bank 2 -> Lanes E, F, G, H
34 * means that the mapping must be determined dynamically, or that the lane
41 /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
57 #define EMI1_SLOT4 4
[all …]
/openbmc/u-boot/board/freescale/t4qds/
H A Deth.c1 // SPDX-License-Identifier: GPL-2.0+
36 #define EMI1_SLOT4 4
57 static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
58 static u8 slot_qsgmii_phyaddr[5][4] = {
61 {4, 5, 6, 7},
101 brdcfg4 = QIXIS_READ(brdcfg[4]); in t4240qds_mux_mdio()
104 QIXIS_WRITE(brdcfg[4], brdcfg4); in t4240qds_mux_mdio()
111 struct t4240qds_mdio *priv = bus->priv; in t4240qds_mdio_read()
113 t4240qds_mux_mdio(priv->muxval); in t4240qds_mdio_read()
115 return priv->realbus->read(priv->realbus, addr, devad, regnum); in t4240qds_mdio_read()
[all …]
/openbmc/u-boot/drivers/phy/marvell/
H A Dcomphy_a3700.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Marvell International Ltd.
17 /* Lane 0 */
19 4,
27 /* Lane 1 */
36 /* Lane 2 */
38 4,
66 /* 0 1 2 3 4 5 6 7 */
67 /*-----------------------------------------------------------*/
144 for (timeout = PLL_LOCK_TIMEOUT; timeout > 0; timeout--) { in comphy_poll_reg()
[all …]
H A Dcomphy_cp110.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Marvell International Ltd.
19 #define SD_ADDR(base, lane) (base + 0x1000 * lane) argument
20 #define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800) argument
21 #define COMPHY_ADDR(base, lane) (base + 0x28 * lane) argument
31 * For CP-110 we have 2 Selector registers "PHY Selectors",
39 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */
41 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */
43 {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */
46 {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */
[all …]
/openbmc/linux/drivers/phy/
H A Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
[all …]
/openbmc/linux/drivers/phy/xilinx/
H A Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
29 * Lane Registers
32 /* TX De-emphasis parameters */
48 #define L0_TXPMD_TM_45_OVER_DP_POST2 BIT(4)
82 #define L0_Ln_REF_CLK_SEL(n) (0x2860 + (n) * 4)
95 #define L3_NSW_PIPE_SHIFT 4
105 #define PLL_REF_SEL(n) (0x10000 + (n) * 4)
[all …]
/openbmc/u-boot/board/freescale/corenet_ds/
H A Deth_p4080.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
59 * that the mapping must be determined dynamically, or that the lane maps to
63 1, 1, 2, 2, 3, 3, 3, 3, 6, 6, 4, 4, 4, 4, 5, 5, 5, 5
94 if (phydev->drv->config) in board_phy_config()
95 phydev->drv->config(phydev); in board_phy_config()
96 if (phydev->drv->uid == PHY_UID_TN2020) { in board_phy_config()
104 while (--timeout) { in board_phy_config()
108 "address %u\n", phydev->addr); in board_phy_config()
122 " to reset.\n", phydev->addr); in board_phy_config()
[all …]
H A Deth_superhydra.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
10 * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
11 * provided by the standard Freescale four-port SGMII riser card. The 10Gb
33 * 2) The phy-handle property of each active Ethernet MAC node is set to the
38 * values, so those values are hard-coded in the DTS. On the HYDRA board,
46 * and might need to be enabled, and also might need to have its mux-value
98 * that the mapping must be determined dynamically, or that the lane maps to
112 clrsetbits_8(&pixis->brdcfg1, mask, val); in super_hydra_mux_mdio()
124 struct super_hydra_mdio *priv = bus->priv; in super_hydra_mdio_read()
[all …]
/openbmc/linux/include/linux/phy/
H A Dphy-mipi-dphy.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
13 * MIPI D-PHY phy.
20 * Clock transitions and disable the Clock Lane HS-RX.
30 * send HS clock after the last associated Data Lane has
42 * the transmitter prior to any associated Data Lane beginning
53 * Lane LP-00 Line state immediately before the HS-0 Line
65 * should ignore any Clock Lane HS transitions, starting from
76 * Time, in picoseconds, for the Clock Lane receiver to enable
86 * Time, in picoseconds, that the transmitter drives the HS-0
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Darmada-8040-mcbin.dts1 // SPDX-License-Identifier: GPL-2.0
6 #include "armada-8040.dtsi" /* include SoC device tree */
9 model = "MACCHIATOBin-8040";
10 compatible = "marvell,armada8040-mcbin",
14 stdout-path = "serial0:115200n8";
31 simple-bus {
32 compatible = "simple-bus";
33 #address-cells = <1>;
34 #size-cells = <0>;
36 reg_usb3h0_vbus: usb3-vbus0 {
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc86xx/
H A Dmpc8610_serdes.c1 // SPDX-License-Identifier: GPL-2.0+
12 #define SRDS1_MAX_LANES 4
13 #define SRDS2_MAX_LANES 4
50 ccsr_gur_t *gur = &immap->im_gur; in fsl_serdes_init()
51 u32 pordevsr = in_be32(&gur->pordevsr); in fsl_serdes_init()
54 int lane; in fsl_serdes_init() local
66 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
67 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
79 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
80 enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()

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