1 // SPDX-License-Identifier: GPL-2.0+
26 #define EMI1_SLOT3	4
42 /* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
43 static u8 lane_to_slot[] = {1, 2, 3, 4};
85 		brdcfg4 = QIXIS_READ(brdcfg[4]);  in ls1043aqds_mux_mdio()
88 		QIXIS_WRITE(brdcfg[4], brdcfg4);  in ls1043aqds_mux_mdio()
95 	struct ls1043aqds_mdio *priv = bus->priv;  in ls1043aqds_mdio_read()
97 	ls1043aqds_mux_mdio(priv->muxval);  in ls1043aqds_mdio_read()
99 	return priv->realbus->read(priv->realbus, addr, devad, regnum);  in ls1043aqds_mdio_read()
105 	struct ls1043aqds_mdio *priv = bus->priv;  in ls1043aqds_mdio_write()
107 	ls1043aqds_mux_mdio(priv->muxval);  in ls1043aqds_mdio_write()
109 	return priv->realbus->write(priv->realbus, addr, devad,  in ls1043aqds_mdio_write()
115 	struct ls1043aqds_mdio *priv = bus->priv;  in ls1043aqds_mdio_reset()
117 	return priv->realbus->reset(priv->realbus);  in ls1043aqds_mdio_reset()
127 		return -1;  in ls1043aqds_mdio_init()
134 		return -1;  in ls1043aqds_mdio_init()
137 	bus->read = ls1043aqds_mdio_read;  in ls1043aqds_mdio_init()
138 	bus->write = ls1043aqds_mdio_write;  in ls1043aqds_mdio_init()
139 	bus->reset = ls1043aqds_mdio_reset;  in ls1043aqds_mdio_init()
140 	strcpy(bus->name, ls1043aqds_mdio_name_for_muxval(muxval));  in ls1043aqds_mdio_init()
142 	pmdio->realbus = miiphy_get_dev_by_name(realbusname);  in ls1043aqds_mdio_init()
144 	if (!pmdio->realbus) {  in ls1043aqds_mdio_init()
148 		return -1;  in ls1043aqds_mdio_init()
151 	pmdio->muxval = muxval;  in ls1043aqds_mdio_init()
152 	bus->priv = pmdio;  in ls1043aqds_mdio_init()
184 		fdt_delprop(fdt, offset, "phy-handle");  in board_ft_fman_fixup_port()
185 		fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));  in board_ft_fman_fixup_port()
186 		fdt_setprop_string(fdt, offset, "phy-connection-type",  in board_ft_fman_fixup_port()
187 				   "sgmii-2500");  in board_ft_fman_fixup_port()
237 		fdt_delprop(fdt, offset, "phy-connection-type");  in board_ft_fman_fixup_port()
238 		fdt_setprop_string(fdt, offset, "phy-connection-type",  in board_ft_fman_fixup_port()
249 		fdt_delprop(fdt, offset, "phy-handle");  in board_ft_fman_fixup_port()
250 		fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));  in board_ft_fman_fixup_port()
251 		fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");  in board_ft_fman_fixup_port()
261 	srds_s1 = in_be32(&gur->rcwsr[4]) &  in fdt_fixup_board_enet()
297 	int i, idx, lane, slot, interface;  in board_eth_init()  local
303 	srds_s1 = in_be32(&gur->rcwsr[4]) &  in board_eth_init()
326 	/* Register the muxing front-ends to the MDIO buses */  in board_eth_init()
335 	/* Set the two on-board RGMII PHY address */  in board_eth_init()
341 		/* 2.5G SGMII on lane A, MAC 9 */  in board_eth_init()
346 		/* QSGMII on lane A, MAC 1/2/5/6 */  in board_eth_init()
357 		/* SGMII on lane B, MAC 2*/  in board_eth_init()
361 		/* 2.5G SGMII on lane A, MAC 9 */  in board_eth_init()
363 		/* SGMII on lane B, MAC 2*/  in board_eth_init()
367 		/* SGMII on lane C, MAC 5 */  in board_eth_init()
371 		/* SGMII on lane B, MAC 2 */  in board_eth_init()
375 		/* SGMII on lane A, MAC 9 */  in board_eth_init()
379 		/* QSGMII on lane B, MAC 1/2/5/6 */  in board_eth_init()
390 		/* 2.5G SGMII on lane A, MAC 9 */  in board_eth_init()
392 		/* QSGMII on lane B, MAC 1/2/5/6 */  in board_eth_init()
403 		/* 2.5G SGMII on lane A, MAC 9 */  in board_eth_init()
405 		/* 2.5G SGMII on lane B, MAC 2 */  in board_eth_init()
409 		/* SGMII on lane A/B/C/D, MAC 9/2/5/6 */  in board_eth_init()
426 		idx = i - FM1_DTSEC1;  in board_eth_init()
433 				lane = serdes_get_first_lane(FSL_SRDS_1,  in board_eth_init()
436 				lane = serdes_get_first_lane(FSL_SRDS_1,  in board_eth_init()
439 				lane = serdes_get_first_lane(FSL_SRDS_1,  in board_eth_init()
443 			if (lane < 0)  in board_eth_init()
446 			slot = lane_to_slot[lane];  in board_eth_init()
449 			if (QIXIS_READ(present2) & (1 << (slot - 1)))  in board_eth_init()
468 			case 4:  in board_eth_init()