1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2012 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <command.h>
8 #include <netdev.h>
9 #include <asm/mmu.h>
10 #include <asm/processor.h>
11 #include <asm/cache.h>
12 #include <asm/immap_85xx.h>
13 #include <asm/fsl_law.h>
14 #include <fsl_ddr_sdram.h>
15 #include <asm/fsl_serdes.h>
16 #include <asm/fsl_portals.h>
17 #include <asm/fsl_liodn.h>
18 #include <malloc.h>
19 #include <fm_eth.h>
20 #include <fsl_mdio.h>
21 #include <miiphy.h>
22 #include <phy.h>
23 #include <fsl_dtsec.h>
24 #include <asm/fsl_serdes.h>
25 #include <hwconfig.h>
26 #include "../common/qixis.h"
27 #include "../common/fman.h"
28
29 #include "t4240qds_qixis.h"
30
31 #define EMI_NONE 0xFFFFFFFF
32 #define EMI1_RGMII 0
33 #define EMI1_SLOT1 1
34 #define EMI1_SLOT2 2
35 #define EMI1_SLOT3 3
36 #define EMI1_SLOT4 4
37 #define EMI1_SLOT5 5
38 #define EMI1_SLOT7 7
39 #define EMI2 8
40 /* Slot6 and Slot8 do not have EMI connections */
41
42 static int mdio_mux[NUM_FM_PORTS];
43
44 static const char *mdio_names[] = {
45 "T4240QDS_MDIO0",
46 "T4240QDS_MDIO1",
47 "T4240QDS_MDIO2",
48 "T4240QDS_MDIO3",
49 "T4240QDS_MDIO4",
50 "T4240QDS_MDIO5",
51 "NULL",
52 "T4240QDS_MDIO7",
53 "T4240QDS_10GC",
54 };
55
56 static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
57 static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
58 static u8 slot_qsgmii_phyaddr[5][4] = {
59 {0, 0, 0, 0},/* not used, to make index match slot No. */
60 {0, 1, 2, 3},
61 {4, 5, 6, 7},
62 {8, 9, 0xa, 0xb},
63 {0xc, 0xd, 0xe, 0xf},
64 };
65 static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0};
66
t4240qds_mdio_name_for_muxval(u8 muxval)67 static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
68 {
69 return mdio_names[muxval];
70 }
71
mii_dev_for_muxval(u8 muxval)72 struct mii_dev *mii_dev_for_muxval(u8 muxval)
73 {
74 struct mii_dev *bus;
75 const char *name = t4240qds_mdio_name_for_muxval(muxval);
76
77 if (!name) {
78 printf("No bus for muxval %x\n", muxval);
79 return NULL;
80 }
81
82 bus = miiphy_get_dev_by_name(name);
83
84 if (!bus) {
85 printf("No bus by name %s\n", name);
86 return NULL;
87 }
88
89 return bus;
90 }
91
92 struct t4240qds_mdio {
93 u8 muxval;
94 struct mii_dev *realbus;
95 };
96
t4240qds_mux_mdio(u8 muxval)97 static void t4240qds_mux_mdio(u8 muxval)
98 {
99 u8 brdcfg4;
100 if ((muxval < 6) || (muxval == 7)) {
101 brdcfg4 = QIXIS_READ(brdcfg[4]);
102 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
103 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
104 QIXIS_WRITE(brdcfg[4], brdcfg4);
105 }
106 }
107
t4240qds_mdio_read(struct mii_dev * bus,int addr,int devad,int regnum)108 static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad,
109 int regnum)
110 {
111 struct t4240qds_mdio *priv = bus->priv;
112
113 t4240qds_mux_mdio(priv->muxval);
114
115 return priv->realbus->read(priv->realbus, addr, devad, regnum);
116 }
117
t4240qds_mdio_write(struct mii_dev * bus,int addr,int devad,int regnum,u16 value)118 static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad,
119 int regnum, u16 value)
120 {
121 struct t4240qds_mdio *priv = bus->priv;
122
123 t4240qds_mux_mdio(priv->muxval);
124
125 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
126 }
127
t4240qds_mdio_reset(struct mii_dev * bus)128 static int t4240qds_mdio_reset(struct mii_dev *bus)
129 {
130 struct t4240qds_mdio *priv = bus->priv;
131
132 return priv->realbus->reset(priv->realbus);
133 }
134
t4240qds_mdio_init(char * realbusname,u8 muxval)135 static int t4240qds_mdio_init(char *realbusname, u8 muxval)
136 {
137 struct t4240qds_mdio *pmdio;
138 struct mii_dev *bus = mdio_alloc();
139
140 if (!bus) {
141 printf("Failed to allocate T4240QDS MDIO bus\n");
142 return -1;
143 }
144
145 pmdio = malloc(sizeof(*pmdio));
146 if (!pmdio) {
147 printf("Failed to allocate T4240QDS private data\n");
148 free(bus);
149 return -1;
150 }
151
152 bus->read = t4240qds_mdio_read;
153 bus->write = t4240qds_mdio_write;
154 bus->reset = t4240qds_mdio_reset;
155 strcpy(bus->name, t4240qds_mdio_name_for_muxval(muxval));
156
157 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
158
159 if (!pmdio->realbus) {
160 printf("No bus with name %s\n", realbusname);
161 free(bus);
162 free(pmdio);
163 return -1;
164 }
165
166 pmdio->muxval = muxval;
167 bus->priv = pmdio;
168
169 return mdio_register(bus);
170 }
171
board_ft_fman_fixup_port(void * blob,char * prop,phys_addr_t pa,enum fm_port port,int offset)172 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
173 enum fm_port port, int offset)
174 {
175 int interface = fm_info_get_enet_if(port);
176 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
177 u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
178
179 prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
180
181 if (interface == PHY_INTERFACE_MODE_SGMII ||
182 interface == PHY_INTERFACE_MODE_QSGMII) {
183 switch (port) {
184 case FM1_DTSEC1:
185 if (qsgmiiphy_fix[port])
186 fdt_set_phy_handle(blob, prop, pa,
187 "sgmii_phy21");
188 break;
189 case FM1_DTSEC2:
190 if (qsgmiiphy_fix[port])
191 fdt_set_phy_handle(blob, prop, pa,
192 "sgmii_phy22");
193 break;
194 case FM1_DTSEC3:
195 if (qsgmiiphy_fix[port])
196 fdt_set_phy_handle(blob, prop, pa,
197 "sgmii_phy23");
198 break;
199 case FM1_DTSEC4:
200 if (qsgmiiphy_fix[port])
201 fdt_set_phy_handle(blob, prop, pa,
202 "sgmii_phy24");
203 break;
204 case FM1_DTSEC6:
205 if (qsgmiiphy_fix[port])
206 fdt_set_phy_handle(blob, prop, pa,
207 "sgmii_phy12");
208 break;
209 case FM1_DTSEC9:
210 if (qsgmiiphy_fix[port])
211 fdt_set_phy_handle(blob, prop, pa,
212 "sgmii_phy14");
213 else
214 fdt_set_phy_handle(blob, prop, pa,
215 "phy_sgmii4");
216 break;
217 case FM1_DTSEC10:
218 if (qsgmiiphy_fix[port])
219 fdt_set_phy_handle(blob, prop, pa,
220 "sgmii_phy13");
221 else
222 fdt_set_phy_handle(blob, prop, pa,
223 "phy_sgmii3");
224 break;
225 case FM2_DTSEC1:
226 if (qsgmiiphy_fix[port])
227 fdt_set_phy_handle(blob, prop, pa,
228 "sgmii_phy41");
229 break;
230 case FM2_DTSEC2:
231 if (qsgmiiphy_fix[port])
232 fdt_set_phy_handle(blob, prop, pa,
233 "sgmii_phy42");
234 break;
235 case FM2_DTSEC3:
236 if (qsgmiiphy_fix[port])
237 fdt_set_phy_handle(blob, prop, pa,
238 "sgmii_phy43");
239 break;
240 case FM2_DTSEC4:
241 if (qsgmiiphy_fix[port])
242 fdt_set_phy_handle(blob, prop, pa,
243 "sgmii_phy44");
244 break;
245 case FM2_DTSEC6:
246 if (qsgmiiphy_fix[port])
247 fdt_set_phy_handle(blob, prop, pa,
248 "sgmii_phy32");
249 break;
250 case FM2_DTSEC9:
251 if (qsgmiiphy_fix[port])
252 fdt_set_phy_handle(blob, prop, pa,
253 "sgmii_phy34");
254 else
255 fdt_set_phy_handle(blob, prop, pa,
256 "phy_sgmii12");
257 break;
258 case FM2_DTSEC10:
259 if (qsgmiiphy_fix[port])
260 fdt_set_phy_handle(blob, prop, pa,
261 "sgmii_phy33");
262 else
263 fdt_set_phy_handle(blob, prop, pa,
264 "phy_sgmii11");
265 break;
266 default:
267 break;
268 }
269 } else if (interface == PHY_INTERFACE_MODE_XGMII &&
270 ((prtcl2 == 55) || (prtcl2 == 57))) {
271 /*
272 * if the 10G is XFI, check hwconfig to see what is the
273 * media type, there are two types, fiber or copper,
274 * fix the dtb accordingly.
275 */
276 int media_type = 0;
277 struct fixed_link f_link;
278 char lane_mode[20] = {"10GBASE-KR"};
279 char buf[32] = "serdes-2,";
280 int off;
281
282 switch (port) {
283 case FM1_10GEC1:
284 if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
285 media_type = 1;
286 fdt_set_phy_handle(blob, prop, pa,
287 "phy_xfi1");
288 sprintf(buf, "%s%s%s", buf, "lane-a,",
289 (char *)lane_mode);
290 }
291 break;
292 case FM1_10GEC2:
293 if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
294 media_type = 1;
295 fdt_set_phy_handle(blob, prop, pa,
296 "phy_xfi2");
297 sprintf(buf, "%s%s%s", buf, "lane-b,",
298 (char *)lane_mode);
299 }
300 break;
301 case FM2_10GEC1:
302 if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g1")) {
303 media_type = 1;
304 fdt_set_phy_handle(blob, prop, pa,
305 "phy_xfi3");
306 sprintf(buf, "%s%s%s", buf, "lane-d,",
307 (char *)lane_mode);
308 }
309 break;
310 case FM2_10GEC2:
311 if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g2")) {
312 media_type = 1;
313 fdt_set_phy_handle(blob, prop, pa,
314 "phy_xfi4");
315 sprintf(buf, "%s%s%s", buf, "lane-c,",
316 (char *)lane_mode);
317 }
318 break;
319 default:
320 return;
321 }
322
323 if (!media_type) {
324 /* fixed-link is used for XFI fiber cable */
325 fdt_delprop(blob, offset, "phy-handle");
326 f_link.phy_id = port;
327 f_link.duplex = 1;
328 f_link.link_speed = 10000;
329 f_link.pause = 0;
330 f_link.asym_pause = 0;
331 fdt_setprop(blob, offset, "fixed-link", &f_link,
332 sizeof(f_link));
333 } else {
334 /* set property for copper cable */
335 off = fdt_node_offset_by_compat_reg(blob,
336 "fsl,fman-memac-mdio", pa + 0x1000);
337 fdt_setprop_string(blob, off, "lane-instance", buf);
338 }
339 }
340 }
341
fdt_fixup_board_enet(void * fdt)342 void fdt_fixup_board_enet(void *fdt)
343 {
344 int i;
345 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
346 u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
347
348 prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
349 for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
350 switch (fm_info_get_enet_if(i)) {
351 case PHY_INTERFACE_MODE_SGMII:
352 case PHY_INTERFACE_MODE_QSGMII:
353 switch (mdio_mux[i]) {
354 case EMI1_SLOT1:
355 fdt_status_okay_by_alias(fdt, "emi1_slot1");
356 break;
357 case EMI1_SLOT2:
358 fdt_status_okay_by_alias(fdt, "emi1_slot2");
359 break;
360 case EMI1_SLOT3:
361 fdt_status_okay_by_alias(fdt, "emi1_slot3");
362 break;
363 case EMI1_SLOT4:
364 fdt_status_okay_by_alias(fdt, "emi1_slot4");
365 break;
366 default:
367 break;
368 }
369 break;
370 case PHY_INTERFACE_MODE_XGMII:
371 /* check if it's XFI interface for 10g */
372 if ((prtcl2 == 55) || (prtcl2 == 57)) {
373 if (i == FM1_10GEC1 && hwconfig_sub(
374 "fsl_10gkr_copper", "fm1_10g1"))
375 fdt_status_okay_by_alias(
376 fdt, "xfi_pcs_mdio1");
377 if (i == FM1_10GEC2 && hwconfig_sub(
378 "fsl_10gkr_copper", "fm1_10g2"))
379 fdt_status_okay_by_alias(
380 fdt, "xfi_pcs_mdio2");
381 if (i == FM2_10GEC1 && hwconfig_sub(
382 "fsl_10gkr_copper", "fm2_10g1"))
383 fdt_status_okay_by_alias(
384 fdt, "xfi_pcs_mdio3");
385 if (i == FM2_10GEC2 && hwconfig_sub(
386 "fsl_10gkr_copper", "fm2_10g2"))
387 fdt_status_okay_by_alias(
388 fdt, "xfi_pcs_mdio4");
389 break;
390 }
391 switch (i) {
392 case FM1_10GEC1:
393 fdt_status_okay_by_alias(fdt, "emi2_xauislot1");
394 break;
395 case FM1_10GEC2:
396 fdt_status_okay_by_alias(fdt, "emi2_xauislot2");
397 break;
398 case FM2_10GEC1:
399 fdt_status_okay_by_alias(fdt, "emi2_xauislot3");
400 break;
401 case FM2_10GEC2:
402 fdt_status_okay_by_alias(fdt, "emi2_xauislot4");
403 break;
404 default:
405 break;
406 }
407 break;
408 default:
409 break;
410 }
411 }
412 }
413
initialize_qsgmiiphy_fix(void)414 static void initialize_qsgmiiphy_fix(void)
415 {
416 int i;
417 unsigned short reg;
418
419 for (i = 1; i <= 4; i++) {
420 /*
421 * Try to read if a SGMII card is used, we do it slot by slot.
422 * if a SGMII PHY address is valid on a slot, then we mark
423 * all ports on the slot, then fix the PHY address for the
424 * marked port when doing dtb fixup.
425 */
426 if (miiphy_read(mdio_names[i],
427 SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, ®) != 0) {
428 debug("Slot%d PHY ID register 2 read failed\n", i);
429 continue;
430 }
431
432 debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg);
433
434 if (reg == 0xFFFF) {
435 /* No physical device present at this address */
436 continue;
437 }
438
439 switch (i) {
440 case 1:
441 qsgmiiphy_fix[FM1_DTSEC5] = 1;
442 qsgmiiphy_fix[FM1_DTSEC6] = 1;
443 qsgmiiphy_fix[FM1_DTSEC9] = 1;
444 qsgmiiphy_fix[FM1_DTSEC10] = 1;
445 slot_qsgmii_phyaddr[1][0] = SGMII_CARD_PORT1_PHY_ADDR;
446 slot_qsgmii_phyaddr[1][1] = SGMII_CARD_PORT2_PHY_ADDR;
447 slot_qsgmii_phyaddr[1][2] = SGMII_CARD_PORT3_PHY_ADDR;
448 slot_qsgmii_phyaddr[1][3] = SGMII_CARD_PORT4_PHY_ADDR;
449 break;
450 case 2:
451 qsgmiiphy_fix[FM1_DTSEC1] = 1;
452 qsgmiiphy_fix[FM1_DTSEC2] = 1;
453 qsgmiiphy_fix[FM1_DTSEC3] = 1;
454 qsgmiiphy_fix[FM1_DTSEC4] = 1;
455 slot_qsgmii_phyaddr[2][0] = SGMII_CARD_PORT1_PHY_ADDR;
456 slot_qsgmii_phyaddr[2][1] = SGMII_CARD_PORT2_PHY_ADDR;
457 slot_qsgmii_phyaddr[2][2] = SGMII_CARD_PORT3_PHY_ADDR;
458 slot_qsgmii_phyaddr[2][3] = SGMII_CARD_PORT4_PHY_ADDR;
459 break;
460 case 3:
461 qsgmiiphy_fix[FM2_DTSEC5] = 1;
462 qsgmiiphy_fix[FM2_DTSEC6] = 1;
463 qsgmiiphy_fix[FM2_DTSEC9] = 1;
464 qsgmiiphy_fix[FM2_DTSEC10] = 1;
465 slot_qsgmii_phyaddr[3][0] = SGMII_CARD_PORT1_PHY_ADDR;
466 slot_qsgmii_phyaddr[3][1] = SGMII_CARD_PORT2_PHY_ADDR;
467 slot_qsgmii_phyaddr[3][2] = SGMII_CARD_PORT3_PHY_ADDR;
468 slot_qsgmii_phyaddr[3][3] = SGMII_CARD_PORT4_PHY_ADDR;
469 break;
470 case 4:
471 qsgmiiphy_fix[FM2_DTSEC1] = 1;
472 qsgmiiphy_fix[FM2_DTSEC2] = 1;
473 qsgmiiphy_fix[FM2_DTSEC3] = 1;
474 qsgmiiphy_fix[FM2_DTSEC4] = 1;
475 slot_qsgmii_phyaddr[4][0] = SGMII_CARD_PORT1_PHY_ADDR;
476 slot_qsgmii_phyaddr[4][1] = SGMII_CARD_PORT2_PHY_ADDR;
477 slot_qsgmii_phyaddr[4][2] = SGMII_CARD_PORT3_PHY_ADDR;
478 slot_qsgmii_phyaddr[4][3] = SGMII_CARD_PORT4_PHY_ADDR;
479 break;
480 default:
481 break;
482 }
483 }
484 }
485
board_eth_init(bd_t * bis)486 int board_eth_init(bd_t *bis)
487 {
488 #if defined(CONFIG_FMAN_ENET)
489 int i, idx, lane, slot, interface;
490 struct memac_mdio_info dtsec_mdio_info;
491 struct memac_mdio_info tgec_mdio_info;
492 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
493 u32 srds_prtcl_s1, srds_prtcl_s2;
494
495 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
496 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
497 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
498 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
499 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
500 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
501
502 /* Initialize the mdio_mux array so we can recognize empty elements */
503 for (i = 0; i < NUM_FM_PORTS; i++)
504 mdio_mux[i] = EMI_NONE;
505
506 dtsec_mdio_info.regs =
507 (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
508
509 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
510
511 /* Register the 1G MDIO bus */
512 fm_memac_mdio_init(bis, &dtsec_mdio_info);
513
514 tgec_mdio_info.regs =
515 (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
516 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
517
518 /* Register the 10G MDIO bus */
519 fm_memac_mdio_init(bis, &tgec_mdio_info);
520
521 /* Register the muxing front-ends to the MDIO buses */
522 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
523 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
524 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
525 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
526 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
527 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
528 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
529 t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
530
531 initialize_qsgmiiphy_fix();
532
533 switch (srds_prtcl_s1) {
534 case 1:
535 case 2:
536 case 4:
537 /* XAUI/HiGig in Slot1 and Slot2 */
538 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
539 fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
540 break;
541 case 27:
542 case 28:
543 case 35:
544 case 36:
545 /* SGMII in Slot1 and Slot2 */
546 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
547 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
548 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
549 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
550 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
551 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
552 if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
553 fm_info_set_phy_address(FM1_DTSEC9,
554 slot_qsgmii_phyaddr[1][3]);
555 fm_info_set_phy_address(FM1_DTSEC10,
556 slot_qsgmii_phyaddr[1][2]);
557 }
558 break;
559 case 37:
560 case 38:
561 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
562 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
563 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
564 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
565 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
566 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
567 if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
568 fm_info_set_phy_address(FM1_DTSEC9,
569 slot_qsgmii_phyaddr[1][2]);
570 fm_info_set_phy_address(FM1_DTSEC10,
571 slot_qsgmii_phyaddr[1][3]);
572 }
573 break;
574 case 39:
575 case 40:
576 case 45:
577 case 46:
578 case 47:
579 case 48:
580 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
581 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
582 if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
583 fm_info_set_phy_address(FM1_DTSEC10,
584 slot_qsgmii_phyaddr[1][2]);
585 fm_info_set_phy_address(FM1_DTSEC9,
586 slot_qsgmii_phyaddr[1][3]);
587 }
588 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
589 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
590 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
591 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
592 break;
593 default:
594 puts("Invalid SerDes1 protocol for T4240QDS\n");
595 break;
596 }
597
598 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
599 idx = i - FM1_DTSEC1;
600 interface = fm_info_get_enet_if(i);
601 switch (interface) {
602 case PHY_INTERFACE_MODE_SGMII:
603 case PHY_INTERFACE_MODE_QSGMII:
604 if (interface == PHY_INTERFACE_MODE_QSGMII) {
605 if (idx <= 3)
606 lane = serdes_get_first_lane(FSL_SRDS_1,
607 QSGMII_FM1_A);
608 else
609 lane = serdes_get_first_lane(FSL_SRDS_1,
610 QSGMII_FM1_B);
611 if (lane < 0)
612 break;
613 slot = lane_to_slot_fsm1[lane];
614 debug("FM1@DTSEC%u expects QSGMII in slot %u\n",
615 idx + 1, slot);
616 } else {
617 lane = serdes_get_first_lane(FSL_SRDS_1,
618 SGMII_FM1_DTSEC1 + idx);
619 if (lane < 0)
620 break;
621 slot = lane_to_slot_fsm1[lane];
622 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
623 idx + 1, slot);
624 }
625 if (QIXIS_READ(present2) & (1 << (slot - 1)))
626 fm_disable_port(i);
627 switch (slot) {
628 case 1:
629 mdio_mux[i] = EMI1_SLOT1;
630 fm_info_set_mdio(i,
631 mii_dev_for_muxval(mdio_mux[i]));
632 break;
633 case 2:
634 mdio_mux[i] = EMI1_SLOT2;
635 fm_info_set_mdio(i,
636 mii_dev_for_muxval(mdio_mux[i]));
637 break;
638 };
639 break;
640 case PHY_INTERFACE_MODE_RGMII:
641 /* FM1 DTSEC5 routes to RGMII with EC2 */
642 debug("FM1@DTSEC%u is RGMII at address %u\n",
643 idx + 1, 2);
644 if (i == FM1_DTSEC5)
645 fm_info_set_phy_address(i, 2);
646 mdio_mux[i] = EMI1_RGMII;
647 fm_info_set_mdio(i,
648 mii_dev_for_muxval(mdio_mux[i]));
649 break;
650 default:
651 break;
652 }
653 }
654
655 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
656 idx = i - FM1_10GEC1;
657 switch (fm_info_get_enet_if(i)) {
658 case PHY_INTERFACE_MODE_XGMII:
659 if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
660 /* A fake PHY address to make U-Boot happy */
661 fm_info_set_phy_address(i, i);
662 } else {
663 lane = serdes_get_first_lane(FSL_SRDS_1,
664 XAUI_FM1_MAC9 + idx);
665 if (lane < 0)
666 break;
667 slot = lane_to_slot_fsm1[lane];
668 if (QIXIS_READ(present2) & (1 << (slot - 1)))
669 fm_disable_port(i);
670 }
671 mdio_mux[i] = EMI2;
672 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
673 break;
674 default:
675 break;
676 }
677 }
678
679 #if (CONFIG_SYS_NUM_FMAN == 2)
680 switch (srds_prtcl_s2) {
681 case 1:
682 case 2:
683 case 4:
684 /* XAUI/HiGig in Slot3 and Slot4 */
685 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
686 fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
687 break;
688 case 6:
689 case 7:
690 case 12:
691 case 13:
692 case 14:
693 case 15:
694 case 16:
695 case 21:
696 case 22:
697 case 23:
698 case 24:
699 case 25:
700 case 26:
701 /* XAUI/HiGig in Slot3, SGMII in Slot4 */
702 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
703 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
704 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
705 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
706 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
707 break;
708 case 27:
709 case 28:
710 case 35:
711 case 36:
712 /* SGMII in Slot3 and Slot4 */
713 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
714 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
715 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
716 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
717 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
718 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
719 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
720 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
721 break;
722 case 37:
723 case 38:
724 /* QSGMII in Slot3 and Slot4 */
725 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
726 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
727 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
728 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
729 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
730 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
731 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]);
732 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]);
733 break;
734 case 39:
735 case 40:
736 case 45:
737 case 46:
738 case 47:
739 case 48:
740 /* SGMII in Slot3 */
741 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
742 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
743 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
744 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
745 /* QSGMII in Slot4 */
746 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
747 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
748 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
749 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
750 break;
751 case 49:
752 case 50:
753 case 51:
754 case 52:
755 case 53:
756 case 54:
757 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
758 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
759 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
760 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
761 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
762 break;
763 case 55:
764 case 57:
765 /* XFI in Slot3, SGMII in Slot4 */
766 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
767 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
768 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
769 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
770 break;
771 default:
772 puts("Invalid SerDes2 protocol for T4240QDS\n");
773 break;
774 }
775
776 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
777 idx = i - FM2_DTSEC1;
778 interface = fm_info_get_enet_if(i);
779 switch (interface) {
780 case PHY_INTERFACE_MODE_SGMII:
781 case PHY_INTERFACE_MODE_QSGMII:
782 if (interface == PHY_INTERFACE_MODE_QSGMII) {
783 if (idx <= 3)
784 lane = serdes_get_first_lane(FSL_SRDS_2,
785 QSGMII_FM2_A);
786 else
787 lane = serdes_get_first_lane(FSL_SRDS_2,
788 QSGMII_FM2_B);
789 if (lane < 0)
790 break;
791 slot = lane_to_slot_fsm2[lane];
792 debug("FM2@DTSEC%u expects QSGMII in slot %u\n",
793 idx + 1, slot);
794 } else {
795 lane = serdes_get_first_lane(FSL_SRDS_2,
796 SGMII_FM2_DTSEC1 + idx);
797 if (lane < 0)
798 break;
799 slot = lane_to_slot_fsm2[lane];
800 debug("FM2@DTSEC%u expects SGMII in slot %u\n",
801 idx + 1, slot);
802 }
803 if (QIXIS_READ(present2) & (1 << (slot - 1)))
804 fm_disable_port(i);
805 switch (slot) {
806 case 3:
807 mdio_mux[i] = EMI1_SLOT3;
808 fm_info_set_mdio(i,
809 mii_dev_for_muxval(mdio_mux[i]));
810 break;
811 case 4:
812 mdio_mux[i] = EMI1_SLOT4;
813 fm_info_set_mdio(i,
814 mii_dev_for_muxval(mdio_mux[i]));
815 break;
816 };
817 break;
818 case PHY_INTERFACE_MODE_RGMII:
819 /*
820 * If DTSEC5 is RGMII, then it's routed via via EC1 to
821 * the first on-board RGMII port. If DTSEC6 is RGMII,
822 * then it's routed via via EC2 to the second on-board
823 * RGMII port.
824 */
825 debug("FM2@DTSEC%u is RGMII at address %u\n",
826 idx + 1, i == FM2_DTSEC5 ? 1 : 2);
827 fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);
828 mdio_mux[i] = EMI1_RGMII;
829 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
830 break;
831 default:
832 break;
833 }
834 }
835
836 for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
837 idx = i - FM2_10GEC1;
838 switch (fm_info_get_enet_if(i)) {
839 case PHY_INTERFACE_MODE_XGMII:
840 if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
841 /* A fake PHY address to make U-Boot happy */
842 fm_info_set_phy_address(i, i);
843 } else {
844 lane = serdes_get_first_lane(FSL_SRDS_2,
845 XAUI_FM2_MAC9 + idx);
846 if (lane < 0)
847 break;
848 slot = lane_to_slot_fsm2[lane];
849 if (QIXIS_READ(present2) & (1 << (slot - 1)))
850 fm_disable_port(i);
851 }
852 mdio_mux[i] = EMI2;
853 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
854 break;
855 default:
856 break;
857 }
858 }
859 #endif /* CONFIG_SYS_NUM_FMAN */
860
861 cpu_eth_init(bis);
862 #endif /* CONFIG_FMAN_ENET */
863
864 return pci_eth_init(bis);
865 }
866