1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2d31e53b4STimur Tabi /*
3d31e53b4STimur Tabi * Copyright 2009-2011 Freescale Semiconductor, Inc.
4d31e53b4STimur Tabi * Author: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
5d31e53b4STimur Tabi */
6d31e53b4STimur Tabi
7d31e53b4STimur Tabi /*
8d31e53b4STimur Tabi * This file handles the board muxing between the Fman Ethernet MACs and
9d31e53b4STimur Tabi * the RGMII/SGMII/XGMII PHYs on a Freescale P5040 "Super Hydra" reference
10d31e53b4STimur Tabi * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
11d31e53b4STimur Tabi * provided by the standard Freescale four-port SGMII riser card. The 10Gb
12d31e53b4STimur Tabi * XGMII PHYs are provided via the XAUI riser card. The P5040 has 2 FMans
13d31e53b4STimur Tabi * and 5 1G interfaces and 10G interface per FMan. Based on the options in
14d31e53b4STimur Tabi * the RCW, we could have upto 3 SGMII cards and 1 XAUI card at a time.
15d31e53b4STimur Tabi *
16d31e53b4STimur Tabi * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control
17d31e53b4STimur Tabi * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is
18d31e53b4STimur Tabi * always the same (0). The value for SGMII depends on which slot the riser is
19d31e53b4STimur Tabi * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII,
20d31e53b4STimur Tabi * the value is based on which slot the XAUI is inserted in.
21d31e53b4STimur Tabi *
22d31e53b4STimur Tabi * The SERDES configuration is used to determine where the SGMII and XAUI cards
23d31e53b4STimur Tabi * exist, and also which Fman's MACs are routed to which PHYs. So for a given
24d31e53b4STimur Tabi * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed
25d31e53b4STimur Tabi * to PHYs dynamically.
26d31e53b4STimur Tabi *
27d31e53b4STimur Tabi *
28d31e53b4STimur Tabi * This file also updates the device tree in three ways:
29d31e53b4STimur Tabi *
30d31e53b4STimur Tabi * 1) The status of each virtual MDIO node that is referenced by an Ethernet
31d31e53b4STimur Tabi * node is set to "okay".
32d31e53b4STimur Tabi *
33d31e53b4STimur Tabi * 2) The phy-handle property of each active Ethernet MAC node is set to the
34d31e53b4STimur Tabi * appropriate PHY node.
35d31e53b4STimur Tabi *
36d31e53b4STimur Tabi * 3) The "mux value" for each virtual MDIO node is set to the correct value,
37d31e53b4STimur Tabi * if necessary. Some virtual MDIO nodes do not have configurable mux
38d31e53b4STimur Tabi * values, so those values are hard-coded in the DTS. On the HYDRA board,
39d31e53b4STimur Tabi * the virtual MDIO node for the SGMII card needs to be updated.
40d31e53b4STimur Tabi *
41d31e53b4STimur Tabi * For all this to work, the device tree needs to have the following:
42d31e53b4STimur Tabi *
43d31e53b4STimur Tabi * 1) An alias for each PHY node that an Ethernet node could be routed to.
44d31e53b4STimur Tabi *
45d31e53b4STimur Tabi * 2) An alias for each real and virtual MDIO node that is disabled by default
46d31e53b4STimur Tabi * and might need to be enabled, and also might need to have its mux-value
47d31e53b4STimur Tabi * updated.
48d31e53b4STimur Tabi */
49d31e53b4STimur Tabi
50d31e53b4STimur Tabi #include <common.h>
51d31e53b4STimur Tabi #include <netdev.h>
52d31e53b4STimur Tabi #include <asm/fsl_serdes.h>
53d31e53b4STimur Tabi #include <fm_eth.h>
54d31e53b4STimur Tabi #include <fsl_mdio.h>
55d31e53b4STimur Tabi #include <malloc.h>
56d31e53b4STimur Tabi #include <fdt_support.h>
578225b2fdSShaohui Xie #include <fsl_dtsec.h>
58d31e53b4STimur Tabi
59d31e53b4STimur Tabi #include "../common/ngpixis.h"
60d31e53b4STimur Tabi #include "../common/fman.h"
61d31e53b4STimur Tabi
62d31e53b4STimur Tabi #ifdef CONFIG_FMAN_ENET
63d31e53b4STimur Tabi
64d31e53b4STimur Tabi #define BRDCFG1_EMI1_SEL_MASK 0x70
65d31e53b4STimur Tabi #define BRDCFG1_EMI1_SEL_SLOT1 0x10
66d31e53b4STimur Tabi #define BRDCFG1_EMI1_SEL_SLOT2 0x20
67d31e53b4STimur Tabi #define BRDCFG1_EMI1_SEL_SLOT5 0x30
68d31e53b4STimur Tabi #define BRDCFG1_EMI1_SEL_SLOT6 0x40
69d31e53b4STimur Tabi #define BRDCFG1_EMI1_SEL_SLOT7 0x50
70d31e53b4STimur Tabi #define BRDCFG1_EMI1_SEL_SLOT3 0x60
71d31e53b4STimur Tabi #define BRDCFG1_EMI1_SEL_RGMII 0x00
72d31e53b4STimur Tabi #define BRDCFG1_EMI1_EN 0x08
73d31e53b4STimur Tabi #define BRDCFG1_EMI2_SEL_MASK 0x06
74d31e53b4STimur Tabi #define BRDCFG1_EMI2_SEL_SLOT1 0x00
75d31e53b4STimur Tabi #define BRDCFG1_EMI2_SEL_SLOT2 0x02
76d31e53b4STimur Tabi
77d31e53b4STimur Tabi #define BRDCFG2_REG_GPIO_SEL 0x20
78d31e53b4STimur Tabi
79ffee1ddeSZhao Qiang /* SGMII */
80ffee1ddeSZhao Qiang #define PHY_BASE_ADDR 0x00
81ffee1ddeSZhao Qiang #define REGNUM 0x00
82ffee1ddeSZhao Qiang #define PORT_NUM_FM1 0x04
83ffee1ddeSZhao Qiang #define PORT_NUM_FM2 0x02
84ffee1ddeSZhao Qiang
85d31e53b4STimur Tabi /*
86d31e53b4STimur Tabi * BRDCFG1 mask and value for each MAC
87d31e53b4STimur Tabi *
88d31e53b4STimur Tabi * This array contains the BRDCFG1 values (in mask/val format) that route the
89d31e53b4STimur Tabi * MDIO bus to a particular RGMII or SGMII PHY.
90d31e53b4STimur Tabi */
91d31e53b4STimur Tabi static struct {
92d31e53b4STimur Tabi u8 mask;
93d31e53b4STimur Tabi u8 val;
94d31e53b4STimur Tabi } mdio_mux[NUM_FM_PORTS];
95d31e53b4STimur Tabi
96d31e53b4STimur Tabi /*
97d31e53b4STimur Tabi * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
98d31e53b4STimur Tabi * that the mapping must be determined dynamically, or that the lane maps to
99d31e53b4STimur Tabi * something other than a board slot
100d31e53b4STimur Tabi */
101d31e53b4STimur Tabi static u8 lane_to_slot[] = {
102d31e53b4STimur Tabi 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0
103d31e53b4STimur Tabi };
104d31e53b4STimur Tabi
105d31e53b4STimur Tabi /*
106d31e53b4STimur Tabi * Set the board muxing for a given MAC
107d31e53b4STimur Tabi *
108d31e53b4STimur Tabi * The MDIO layer calls this function every time it wants to talk to a PHY.
109d31e53b4STimur Tabi */
super_hydra_mux_mdio(u8 mask,u8 val)110d31e53b4STimur Tabi void super_hydra_mux_mdio(u8 mask, u8 val)
111d31e53b4STimur Tabi {
112d31e53b4STimur Tabi clrsetbits_8(&pixis->brdcfg1, mask, val);
113d31e53b4STimur Tabi }
114d31e53b4STimur Tabi
115d31e53b4STimur Tabi struct super_hydra_mdio {
116d31e53b4STimur Tabi u8 mask;
117d31e53b4STimur Tabi u8 val;
118d31e53b4STimur Tabi struct mii_dev *realbus;
119d31e53b4STimur Tabi };
120d31e53b4STimur Tabi
super_hydra_mdio_read(struct mii_dev * bus,int addr,int devad,int regnum)121d31e53b4STimur Tabi static int super_hydra_mdio_read(struct mii_dev *bus, int addr, int devad,
122d31e53b4STimur Tabi int regnum)
123d31e53b4STimur Tabi {
124d31e53b4STimur Tabi struct super_hydra_mdio *priv = bus->priv;
125d31e53b4STimur Tabi
126d31e53b4STimur Tabi super_hydra_mux_mdio(priv->mask, priv->val);
127d31e53b4STimur Tabi
128d31e53b4STimur Tabi return priv->realbus->read(priv->realbus, addr, devad, regnum);
129d31e53b4STimur Tabi }
130d31e53b4STimur Tabi
super_hydra_mdio_write(struct mii_dev * bus,int addr,int devad,int regnum,u16 value)131d31e53b4STimur Tabi static int super_hydra_mdio_write(struct mii_dev *bus, int addr, int devad,
132d31e53b4STimur Tabi int regnum, u16 value)
133d31e53b4STimur Tabi {
134d31e53b4STimur Tabi struct super_hydra_mdio *priv = bus->priv;
135d31e53b4STimur Tabi
136d31e53b4STimur Tabi super_hydra_mux_mdio(priv->mask, priv->val);
137d31e53b4STimur Tabi
138d31e53b4STimur Tabi return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
139d31e53b4STimur Tabi }
140d31e53b4STimur Tabi
super_hydra_mdio_reset(struct mii_dev * bus)141d31e53b4STimur Tabi static int super_hydra_mdio_reset(struct mii_dev *bus)
142d31e53b4STimur Tabi {
143d31e53b4STimur Tabi struct super_hydra_mdio *priv = bus->priv;
144d31e53b4STimur Tabi
145d31e53b4STimur Tabi return priv->realbus->reset(priv->realbus);
146d31e53b4STimur Tabi }
147d31e53b4STimur Tabi
super_hydra_mdio_set_mux(char * name,u8 mask,u8 val)148d31e53b4STimur Tabi static void super_hydra_mdio_set_mux(char *name, u8 mask, u8 val)
149d31e53b4STimur Tabi {
150d31e53b4STimur Tabi struct mii_dev *bus = miiphy_get_dev_by_name(name);
151d31e53b4STimur Tabi struct super_hydra_mdio *priv = bus->priv;
152d31e53b4STimur Tabi
153d31e53b4STimur Tabi priv->mask = mask;
154d31e53b4STimur Tabi priv->val = val;
155d31e53b4STimur Tabi }
156d31e53b4STimur Tabi
super_hydra_mdio_init(char * realbusname,char * fakebusname)157d31e53b4STimur Tabi static int super_hydra_mdio_init(char *realbusname, char *fakebusname)
158d31e53b4STimur Tabi {
159d31e53b4STimur Tabi struct super_hydra_mdio *hmdio;
160d31e53b4STimur Tabi struct mii_dev *bus = mdio_alloc();
161d31e53b4STimur Tabi
162d31e53b4STimur Tabi if (!bus) {
163d31e53b4STimur Tabi printf("Failed to allocate Hydra MDIO bus\n");
164d31e53b4STimur Tabi return -1;
165d31e53b4STimur Tabi }
166d31e53b4STimur Tabi
167d31e53b4STimur Tabi hmdio = malloc(sizeof(*hmdio));
168d31e53b4STimur Tabi if (!hmdio) {
169d31e53b4STimur Tabi printf("Failed to allocate Hydra private data\n");
170d31e53b4STimur Tabi free(bus);
171d31e53b4STimur Tabi return -1;
172d31e53b4STimur Tabi }
173d31e53b4STimur Tabi
174d31e53b4STimur Tabi bus->read = super_hydra_mdio_read;
175d31e53b4STimur Tabi bus->write = super_hydra_mdio_write;
176d31e53b4STimur Tabi bus->reset = super_hydra_mdio_reset;
177192bc694SBen Whitten strcpy(bus->name, fakebusname);
178d31e53b4STimur Tabi
179d31e53b4STimur Tabi hmdio->realbus = miiphy_get_dev_by_name(realbusname);
180d31e53b4STimur Tabi
181d31e53b4STimur Tabi if (!hmdio->realbus) {
182d31e53b4STimur Tabi printf("No bus with name %s\n", realbusname);
183d31e53b4STimur Tabi free(bus);
184d31e53b4STimur Tabi free(hmdio);
185d31e53b4STimur Tabi return -1;
186d31e53b4STimur Tabi }
187d31e53b4STimur Tabi
188d31e53b4STimur Tabi bus->priv = hmdio;
189d31e53b4STimur Tabi
190d31e53b4STimur Tabi return mdio_register(bus);
191d31e53b4STimur Tabi }
192d31e53b4STimur Tabi
193d31e53b4STimur Tabi /*
194d31e53b4STimur Tabi * Given the following ...
195d31e53b4STimur Tabi *
196d31e53b4STimur Tabi * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
197d31e53b4STimur Tabi * compatible string and 'addr' physical address)
198d31e53b4STimur Tabi *
199d31e53b4STimur Tabi * 2) An Fman port
200d31e53b4STimur Tabi *
201d31e53b4STimur Tabi * ... update the phy-handle property of the Ethernet node to point to the
202d31e53b4STimur Tabi * right PHY. This assumes that we already know the PHY for each port. That
203d31e53b4STimur Tabi * information is stored in mdio_mux[].
204d31e53b4STimur Tabi *
205d31e53b4STimur Tabi * The offset of the Fman Ethernet node is also passed in for convenience, but
206d31e53b4STimur Tabi * it is not used.
207d31e53b4STimur Tabi *
208d31e53b4STimur Tabi * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
209d31e53b4STimur Tabi * Inside the Fman, "ports" are things that connect to MACs. We only call them
210d31e53b4STimur Tabi * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
211d31e53b4STimur Tabi * and ports are the same thing.
212d31e53b4STimur Tabi */
board_ft_fman_fixup_port(void * fdt,char * compat,phys_addr_t addr,enum fm_port port,int offset)213d31e53b4STimur Tabi void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
214d31e53b4STimur Tabi enum fm_port port, int offset)
215d31e53b4STimur Tabi {
216d31e53b4STimur Tabi enum srds_prtcl device;
217d31e53b4STimur Tabi int lane, slot, phy;
218d31e53b4STimur Tabi char alias[32];
219d31e53b4STimur Tabi
220d31e53b4STimur Tabi /* RGMII and XGMII are already mapped correctly in the DTS */
221d31e53b4STimur Tabi
222d31e53b4STimur Tabi if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
223d31e53b4STimur Tabi device = serdes_device_from_fm_port(port);
224d31e53b4STimur Tabi lane = serdes_get_first_lane(device);
225d31e53b4STimur Tabi slot = lane_to_slot[lane];
226d31e53b4STimur Tabi phy = fm_info_get_phy_address(port);
227d31e53b4STimur Tabi
228d31e53b4STimur Tabi sprintf(alias, "phy_sgmii_slot%u_%x", slot, phy);
229d31e53b4STimur Tabi fdt_set_phy_handle(fdt, compat, addr, alias);
230d31e53b4STimur Tabi }
231d31e53b4STimur Tabi }
232d31e53b4STimur Tabi
233d31e53b4STimur Tabi #define PIXIS_SW2_LANE_23_SEL 0x80
234d31e53b4STimur Tabi #define PIXIS_SW2_LANE_45_SEL 0x40
235d31e53b4STimur Tabi #define PIXIS_SW2_LANE_67_SEL_MASK 0x30
236d31e53b4STimur Tabi #define PIXIS_SW2_LANE_67_SEL_5 0x00
237d31e53b4STimur Tabi #define PIXIS_SW2_LANE_67_SEL_6 0x20
238d31e53b4STimur Tabi #define PIXIS_SW2_LANE_67_SEL_7 0x10
239d31e53b4STimur Tabi #define PIXIS_SW2_LANE_8_SEL 0x08
240d31e53b4STimur Tabi #define PIXIS_SW2_LANE_1617_SEL 0x04
241d31e53b4STimur Tabi #define PIXIS_SW11_LANE_9_SEL 0x04
242d31e53b4STimur Tabi /*
243d31e53b4STimur Tabi * Initialize the lane_to_slot[] array.
244d31e53b4STimur Tabi *
245d31e53b4STimur Tabi * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board
246d31e53b4STimur Tabi * slots is hard-coded. On the Hydra board, however, the mapping is controlled
247d31e53b4STimur Tabi * by board switch SW2, so the lane_to_slot[] array needs to be dynamically
248d31e53b4STimur Tabi * initialized.
249d31e53b4STimur Tabi */
initialize_lane_to_slot(void)250d31e53b4STimur Tabi static void initialize_lane_to_slot(void)
251d31e53b4STimur Tabi {
252d31e53b4STimur Tabi u8 sw2 = in_8(&PIXIS_SW(2));
253d31e53b4STimur Tabi /* SW11 appears in the programming model as SW9 */
254d31e53b4STimur Tabi u8 sw11 = in_8(&PIXIS_SW(9));
255d31e53b4STimur Tabi
256d31e53b4STimur Tabi lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4;
257d31e53b4STimur Tabi lane_to_slot[3] = lane_to_slot[2];
258d31e53b4STimur Tabi
259d31e53b4STimur Tabi lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6;
260d31e53b4STimur Tabi lane_to_slot[5] = lane_to_slot[4];
261d31e53b4STimur Tabi
262d31e53b4STimur Tabi switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) {
263d31e53b4STimur Tabi case PIXIS_SW2_LANE_67_SEL_5:
264d31e53b4STimur Tabi lane_to_slot[6] = 5;
265d31e53b4STimur Tabi break;
266d31e53b4STimur Tabi case PIXIS_SW2_LANE_67_SEL_6:
267d31e53b4STimur Tabi lane_to_slot[6] = 6;
268d31e53b4STimur Tabi break;
269d31e53b4STimur Tabi case PIXIS_SW2_LANE_67_SEL_7:
270d31e53b4STimur Tabi lane_to_slot[6] = 7;
271d31e53b4STimur Tabi break;
272d31e53b4STimur Tabi }
273d31e53b4STimur Tabi lane_to_slot[7] = lane_to_slot[6];
274d31e53b4STimur Tabi
275d31e53b4STimur Tabi lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0;
276d31e53b4STimur Tabi lane_to_slot[9] = (sw11 & PIXIS_SW11_LANE_9_SEL) ? 0 : 3;
277d31e53b4STimur Tabi
278d31e53b4STimur Tabi lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0;
279d31e53b4STimur Tabi lane_to_slot[17] = lane_to_slot[16];
280d31e53b4STimur Tabi }
281d31e53b4STimur Tabi
282d31e53b4STimur Tabi #endif /* #ifdef CONFIG_FMAN_ENET */
283d31e53b4STimur Tabi
284d31e53b4STimur Tabi /*
285d31e53b4STimur Tabi * Configure the status for the virtual MDIO nodes
286d31e53b4STimur Tabi *
287d31e53b4STimur Tabi * Rather than create the virtual MDIO nodes from scratch for each active
288d31e53b4STimur Tabi * virtual MDIO, we expect the DTS to have the nodes defined already, and we
289d31e53b4STimur Tabi * only enable the ones that are actually active.
290d31e53b4STimur Tabi *
291d31e53b4STimur Tabi * We assume that the DTS already hard-codes the status for all the
292d31e53b4STimur Tabi * virtual MDIO nodes to "disabled", so all we need to do is enable the
293d31e53b4STimur Tabi * active ones.
294d31e53b4STimur Tabi */
fdt_fixup_board_enet(void * fdt)295d31e53b4STimur Tabi void fdt_fixup_board_enet(void *fdt)
296d31e53b4STimur Tabi {
297d31e53b4STimur Tabi #ifdef CONFIG_FMAN_ENET
298d31e53b4STimur Tabi enum fm_port i;
299d31e53b4STimur Tabi int lane, slot;
300d31e53b4STimur Tabi
301d31e53b4STimur Tabi for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
302d31e53b4STimur Tabi int idx = i - FM1_DTSEC1;
303d31e53b4STimur Tabi
304d31e53b4STimur Tabi switch (fm_info_get_enet_if(i)) {
305d31e53b4STimur Tabi case PHY_INTERFACE_MODE_SGMII:
306d31e53b4STimur Tabi lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
307d31e53b4STimur Tabi if (lane >= 0) {
308d31e53b4STimur Tabi char alias[32];
309d31e53b4STimur Tabi
310d31e53b4STimur Tabi slot = lane_to_slot[lane];
311d31e53b4STimur Tabi sprintf(alias, "hydra_sg_slot%u", slot);
312d31e53b4STimur Tabi fdt_status_okay_by_alias(fdt, alias);
313d31e53b4STimur Tabi debug("Enabled MDIO node %s (slot %i)\n",
314d31e53b4STimur Tabi alias, slot);
315d31e53b4STimur Tabi }
316d31e53b4STimur Tabi break;
317d31e53b4STimur Tabi case PHY_INTERFACE_MODE_RGMII:
318d31e53b4STimur Tabi fdt_status_okay_by_alias(fdt, "hydra_rg");
319d31e53b4STimur Tabi debug("Enabled MDIO node hydra_rg\n");
320d31e53b4STimur Tabi break;
321d31e53b4STimur Tabi default:
322d31e53b4STimur Tabi break;
323d31e53b4STimur Tabi }
324d31e53b4STimur Tabi }
325d31e53b4STimur Tabi
326d31e53b4STimur Tabi lane = serdes_get_first_lane(XAUI_FM1);
327d31e53b4STimur Tabi if (lane >= 0) {
328d31e53b4STimur Tabi char alias[32];
329d31e53b4STimur Tabi
330d31e53b4STimur Tabi slot = lane_to_slot[lane];
331d31e53b4STimur Tabi sprintf(alias, "hydra_xg_slot%u", slot);
332d31e53b4STimur Tabi fdt_status_okay_by_alias(fdt, alias);
333d31e53b4STimur Tabi debug("Enabled MDIO node %s (slot %i)\n", alias, slot);
334d31e53b4STimur Tabi }
335d31e53b4STimur Tabi
336d31e53b4STimur Tabi #if CONFIG_SYS_NUM_FMAN == 2
337d31e53b4STimur Tabi for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
338d31e53b4STimur Tabi int idx = i - FM2_DTSEC1;
339d31e53b4STimur Tabi
340d31e53b4STimur Tabi switch (fm_info_get_enet_if(i)) {
341d31e53b4STimur Tabi case PHY_INTERFACE_MODE_SGMII:
342d31e53b4STimur Tabi lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
343d31e53b4STimur Tabi if (lane >= 0) {
344d31e53b4STimur Tabi char alias[32];
345d31e53b4STimur Tabi
346d31e53b4STimur Tabi slot = lane_to_slot[lane];
347d31e53b4STimur Tabi sprintf(alias, "hydra_sg_slot%u", slot);
348d31e53b4STimur Tabi fdt_status_okay_by_alias(fdt, alias);
349d31e53b4STimur Tabi debug("Enabled MDIO node %s (slot %i)\n",
350d31e53b4STimur Tabi alias, slot);
351d31e53b4STimur Tabi }
352d31e53b4STimur Tabi break;
353d31e53b4STimur Tabi case PHY_INTERFACE_MODE_RGMII:
354d31e53b4STimur Tabi fdt_status_okay_by_alias(fdt, "hydra_rg");
355d31e53b4STimur Tabi debug("Enabled MDIO node hydra_rg\n");
356d31e53b4STimur Tabi break;
357d31e53b4STimur Tabi default:
358d31e53b4STimur Tabi break;
359d31e53b4STimur Tabi }
360d31e53b4STimur Tabi }
361d31e53b4STimur Tabi
362d31e53b4STimur Tabi lane = serdes_get_first_lane(XAUI_FM2);
363d31e53b4STimur Tabi if (lane >= 0) {
364d31e53b4STimur Tabi char alias[32];
365d31e53b4STimur Tabi
366d31e53b4STimur Tabi slot = lane_to_slot[lane];
367d31e53b4STimur Tabi sprintf(alias, "hydra_xg_slot%u", slot);
368d31e53b4STimur Tabi fdt_status_okay_by_alias(fdt, alias);
369d31e53b4STimur Tabi debug("Enabled MDIO node %s (slot %i)\n", alias, slot);
370d31e53b4STimur Tabi }
371d31e53b4STimur Tabi #endif /* CONFIG_SYS_NUM_FMAN == 2 */
372d31e53b4STimur Tabi #endif /* CONFIG_FMAN_ENET */
373d31e53b4STimur Tabi }
374d31e53b4STimur Tabi
375d31e53b4STimur Tabi /*
376d31e53b4STimur Tabi * Mapping of SerDes Protocol to MDIO MUX value and PHY address.
377d31e53b4STimur Tabi *
378d31e53b4STimur Tabi * Fman 1:
379d31e53b4STimur Tabi * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4
380d31e53b4STimur Tabi * Mux Phy | Mux Phy | Mux Phy | Mux Phy
381d31e53b4STimur Tabi * Value Addr | Value Addr | Value Addr | Value Addr
382d31e53b4STimur Tabi * 0x00 2 1c | 2 1d | 2 1e | 2 1f
383d31e53b4STimur Tabi * 0x01 | | 6 1c |
384d31e53b4STimur Tabi * 0x02 | | 3 1c | 3 1d
385d31e53b4STimur Tabi * 0x03 2 1c | 2 1d | 2 1e | 2 1f
386d31e53b4STimur Tabi * 0x04 2 1c | 2 1d | 2 1e | 2 1f
387d31e53b4STimur Tabi * 0x05 | | 3 1c | 3 1d
388d31e53b4STimur Tabi * 0x06 2 1c | 2 1d | 2 1e | 2 1f
389d31e53b4STimur Tabi * 0x07 | | 6 1c |
390d31e53b4STimur Tabi * 0x11 2 1c | 2 1d | 2 1e | 2 1f
391d31e53b4STimur Tabi * 0x2a 2 | | 2 1e | 2 1f
392d31e53b4STimur Tabi * 0x34 6 1c | 6 1d | 4 1e | 4 1f
393d31e53b4STimur Tabi * 0x35 | | 3 1c | 3 1d
394d31e53b4STimur Tabi * 0x36 6 1c | 6 1d | 4 1e | 4 1f
395d31e53b4STimur Tabi * | | |
396d31e53b4STimur Tabi * Fman 2: | | |
397d31e53b4STimur Tabi * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4
398d31e53b4STimur Tabi * EMI1 | EMI1 | EMI1 | EMI1
399d31e53b4STimur Tabi * Mux Phy | Mux Phy | Mux Phy | Mux Phy
400d31e53b4STimur Tabi * Value Addr | Value Addr | Value Addr | Value Addr
401d31e53b4STimur Tabi * 0x00 | | 6 1c | 6 1d
402d31e53b4STimur Tabi * 0x01 | | |
403d31e53b4STimur Tabi * 0x02 | | 6 1c | 6 1d
404d31e53b4STimur Tabi * 0x03 3 1c | 3 1d | 6 1c | 6 1d
405d31e53b4STimur Tabi * 0x04 3 1c | 3 1d | 6 1c | 6 1d
406d31e53b4STimur Tabi * 0x05 | | 6 1c | 6 1d
407d31e53b4STimur Tabi * 0x06 | | 6 1c | 6 1d
408d31e53b4STimur Tabi * 0x07 | | |
409d31e53b4STimur Tabi * 0x11 | | |
410d31e53b4STimur Tabi * 0x2a | | |
411d31e53b4STimur Tabi * 0x34 | | |
412d31e53b4STimur Tabi * 0x35 | | |
413d31e53b4STimur Tabi * 0x36 | | |
414d31e53b4STimur Tabi */
415d31e53b4STimur Tabi
board_eth_init(bd_t * bis)416d31e53b4STimur Tabi int board_eth_init(bd_t *bis)
417d31e53b4STimur Tabi {
418d31e53b4STimur Tabi #ifdef CONFIG_FMAN_ENET
419d31e53b4STimur Tabi struct fsl_pq_mdio_info dtsec_mdio_info;
420d31e53b4STimur Tabi struct tgec_mdio_info tgec_mdio_info;
421d31e53b4STimur Tabi unsigned int i, slot;
422d31e53b4STimur Tabi int lane;
423ffee1ddeSZhao Qiang struct mii_dev *bus;
424ffee1ddeSZhao Qiang int qsgmii;
425ffee1ddeSZhao Qiang int phy_real_addr;
426d31e53b4STimur Tabi ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
427d31e53b4STimur Tabi int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
428d31e53b4STimur Tabi FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
429d31e53b4STimur Tabi
430d31e53b4STimur Tabi printf("Initializing Fman\n");
431d31e53b4STimur Tabi
432d31e53b4STimur Tabi initialize_lane_to_slot();
433d31e53b4STimur Tabi
434d31e53b4STimur Tabi /* We want to use the PIXIS to configure MUX routing, not GPIOs. */
435d31e53b4STimur Tabi setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);
436d31e53b4STimur Tabi
437d31e53b4STimur Tabi memset(mdio_mux, 0, sizeof(mdio_mux));
438d31e53b4STimur Tabi
439d31e53b4STimur Tabi dtsec_mdio_info.regs =
440d31e53b4STimur Tabi (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
441d31e53b4STimur Tabi dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
442d31e53b4STimur Tabi
443d31e53b4STimur Tabi /* Register the real 1G MDIO bus */
444d31e53b4STimur Tabi fsl_pq_mdio_init(bis, &dtsec_mdio_info);
445d31e53b4STimur Tabi
446d31e53b4STimur Tabi tgec_mdio_info.regs =
447d31e53b4STimur Tabi (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
448d31e53b4STimur Tabi tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
449d31e53b4STimur Tabi
450d31e53b4STimur Tabi /* Register the real 10G MDIO bus */
451d31e53b4STimur Tabi fm_tgec_mdio_init(bis, &tgec_mdio_info);
452d31e53b4STimur Tabi
453d31e53b4STimur Tabi /* Register the three virtual MDIO front-ends */
454d31e53b4STimur Tabi super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
455d31e53b4STimur Tabi "SUPER_HYDRA_RGMII_MDIO");
456d31e53b4STimur Tabi super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
457d31e53b4STimur Tabi "SUPER_HYDRA_FM1_SGMII_MDIO");
458d31e53b4STimur Tabi super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
459d31e53b4STimur Tabi "SUPER_HYDRA_FM2_SGMII_MDIO");
460d5689824SZhao Qiang super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
461d5689824SZhao Qiang "SUPER_HYDRA_FM3_SGMII_MDIO");
462d31e53b4STimur Tabi super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
463d31e53b4STimur Tabi "SUPER_HYDRA_FM1_TGEC_MDIO");
464d31e53b4STimur Tabi super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
465d31e53b4STimur Tabi "SUPER_HYDRA_FM2_TGEC_MDIO");
466d31e53b4STimur Tabi
467d31e53b4STimur Tabi /*
468d31e53b4STimur Tabi * Program the DTSEC PHY addresses assuming that they are all SGMII.
469d31e53b4STimur Tabi * For any DTSEC that's RGMII, we'll override its PHY address later.
470d31e53b4STimur Tabi * We assume that DTSEC5 is only used for RGMII.
471d31e53b4STimur Tabi */
472d31e53b4STimur Tabi fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
473d31e53b4STimur Tabi fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
474d31e53b4STimur Tabi fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
475d31e53b4STimur Tabi
476d31e53b4STimur Tabi #if (CONFIG_SYS_NUM_FMAN == 2)
477d31e53b4STimur Tabi fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
478d31e53b4STimur Tabi fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
479d31e53b4STimur Tabi fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
480d31e53b4STimur Tabi fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
481d31e53b4STimur Tabi fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
482d31e53b4STimur Tabi #endif
483d31e53b4STimur Tabi
484d31e53b4STimur Tabi switch (srds_prtcl) {
485d31e53b4STimur Tabi case 0:
486d31e53b4STimur Tabi case 3:
487d31e53b4STimur Tabi case 4:
488d31e53b4STimur Tabi case 6:
489d31e53b4STimur Tabi case 0x11:
490d31e53b4STimur Tabi case 0x2a:
491d31e53b4STimur Tabi case 0x34:
492d31e53b4STimur Tabi case 0x36:
493d31e53b4STimur Tabi fm_info_set_phy_address(FM1_DTSEC3,
494d31e53b4STimur Tabi CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
495d31e53b4STimur Tabi fm_info_set_phy_address(FM1_DTSEC4,
496d31e53b4STimur Tabi CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
497d31e53b4STimur Tabi break;
498d31e53b4STimur Tabi case 1:
499d31e53b4STimur Tabi case 2:
500d31e53b4STimur Tabi case 5:
501d31e53b4STimur Tabi case 7:
502d31e53b4STimur Tabi case 0x35:
503d31e53b4STimur Tabi fm_info_set_phy_address(FM1_DTSEC3,
504d31e53b4STimur Tabi CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
505d31e53b4STimur Tabi fm_info_set_phy_address(FM1_DTSEC4,
506d31e53b4STimur Tabi CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
507d31e53b4STimur Tabi break;
508d31e53b4STimur Tabi default:
509d31e53b4STimur Tabi printf("Fman: Unsupport SerDes Protocol 0x%02x\n", srds_prtcl);
510d31e53b4STimur Tabi break;
511d31e53b4STimur Tabi }
512d31e53b4STimur Tabi
513d31e53b4STimur Tabi for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
514d31e53b4STimur Tabi int idx = i - FM1_DTSEC1;
515d31e53b4STimur Tabi
516d31e53b4STimur Tabi switch (fm_info_get_enet_if(i)) {
517d31e53b4STimur Tabi case PHY_INTERFACE_MODE_SGMII:
518d31e53b4STimur Tabi lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
519d31e53b4STimur Tabi if (lane < 0)
520d31e53b4STimur Tabi break;
521d31e53b4STimur Tabi slot = lane_to_slot[lane];
522d31e53b4STimur Tabi mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
523d31e53b4STimur Tabi debug("FM1@DTSEC%u expects SGMII in slot %u\n",
524d31e53b4STimur Tabi idx + 1, slot);
525d31e53b4STimur Tabi switch (slot) {
526d31e53b4STimur Tabi case 1:
527d31e53b4STimur Tabi mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
528d31e53b4STimur Tabi BRDCFG1_EMI1_EN;
529d31e53b4STimur Tabi break;
530d31e53b4STimur Tabi case 2:
531d31e53b4STimur Tabi mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
532d31e53b4STimur Tabi BRDCFG1_EMI1_EN;
533d31e53b4STimur Tabi break;
534d31e53b4STimur Tabi case 3:
535d31e53b4STimur Tabi mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 |
536d31e53b4STimur Tabi BRDCFG1_EMI1_EN;
537d31e53b4STimur Tabi break;
538d31e53b4STimur Tabi case 5:
539d31e53b4STimur Tabi mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
540d31e53b4STimur Tabi BRDCFG1_EMI1_EN;
541d31e53b4STimur Tabi break;
542d31e53b4STimur Tabi case 6:
543d31e53b4STimur Tabi mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
544d31e53b4STimur Tabi BRDCFG1_EMI1_EN;
545d31e53b4STimur Tabi break;
546d31e53b4STimur Tabi case 7:
547d31e53b4STimur Tabi mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
548d31e53b4STimur Tabi BRDCFG1_EMI1_EN;
549d31e53b4STimur Tabi break;
550d31e53b4STimur Tabi };
551d31e53b4STimur Tabi
552d31e53b4STimur Tabi super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_SGMII_MDIO",
553d31e53b4STimur Tabi mdio_mux[i].mask, mdio_mux[i].val);
554d31e53b4STimur Tabi fm_info_set_mdio(i,
555d31e53b4STimur Tabi miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"));
556d31e53b4STimur Tabi break;
557d31e53b4STimur Tabi case PHY_INTERFACE_MODE_RGMII:
558d31e53b4STimur Tabi /*
559d31e53b4STimur Tabi * FM1 DTSEC5 is routed via EC1 to the first on-board
560d31e53b4STimur Tabi * RGMII port. FM2 DTSEC5 is routed via EC2 to the
561d31e53b4STimur Tabi * second on-board RGMII port. The other DTSECs cannot
562d31e53b4STimur Tabi * be routed to RGMII.
563d31e53b4STimur Tabi */
564d31e53b4STimur Tabi debug("FM1@DTSEC%u is RGMII at address %u\n",
565d31e53b4STimur Tabi idx + 1, 0);
566d31e53b4STimur Tabi fm_info_set_phy_address(i, 0);
567d31e53b4STimur Tabi mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
568d31e53b4STimur Tabi mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
569d31e53b4STimur Tabi BRDCFG1_EMI1_EN;
570d31e53b4STimur Tabi super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO",
571d31e53b4STimur Tabi mdio_mux[i].mask, mdio_mux[i].val);
572d31e53b4STimur Tabi fm_info_set_mdio(i,
573d31e53b4STimur Tabi miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
574d31e53b4STimur Tabi break;
575d31e53b4STimur Tabi case PHY_INTERFACE_MODE_NONE:
576d31e53b4STimur Tabi fm_info_set_phy_address(i, 0);
577d31e53b4STimur Tabi break;
578d31e53b4STimur Tabi default:
579d31e53b4STimur Tabi printf("Fman1: DTSEC%u set to unknown interface %i\n",
580d31e53b4STimur Tabi idx + 1, fm_info_get_enet_if(i));
581d31e53b4STimur Tabi fm_info_set_phy_address(i, 0);
582d31e53b4STimur Tabi break;
583d31e53b4STimur Tabi }
584d31e53b4STimur Tabi }
585d31e53b4STimur Tabi
586ffee1ddeSZhao Qiang bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO");
587ffee1ddeSZhao Qiang qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM_FM1, REGNUM);
588ffee1ddeSZhao Qiang
589ffee1ddeSZhao Qiang if (qsgmii) {
590ffee1ddeSZhao Qiang for (i = FM1_DTSEC1; i < FM1_DTSEC1 + PORT_NUM_FM1; i++) {
591ffee1ddeSZhao Qiang if (fm_info_get_enet_if(i) ==
592ffee1ddeSZhao Qiang PHY_INTERFACE_MODE_SGMII) {
593ffee1ddeSZhao Qiang phy_real_addr = PHY_BASE_ADDR + i - FM1_DTSEC1;
594ffee1ddeSZhao Qiang fm_info_set_phy_address(i, phy_real_addr);
595ffee1ddeSZhao Qiang }
596ffee1ddeSZhao Qiang }
597ffee1ddeSZhao Qiang switch (srds_prtcl) {
598ffee1ddeSZhao Qiang case 0x00:
599ffee1ddeSZhao Qiang case 0x03:
600ffee1ddeSZhao Qiang case 0x04:
601ffee1ddeSZhao Qiang case 0x06:
602ffee1ddeSZhao Qiang case 0x11:
603ffee1ddeSZhao Qiang case 0x2a:
604ffee1ddeSZhao Qiang case 0x34:
605ffee1ddeSZhao Qiang case 0x36:
606ffee1ddeSZhao Qiang fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 2);
607ffee1ddeSZhao Qiang fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 3);
608ffee1ddeSZhao Qiang break;
609ffee1ddeSZhao Qiang case 0x01:
610ffee1ddeSZhao Qiang case 0x02:
611ffee1ddeSZhao Qiang case 0x05:
612ffee1ddeSZhao Qiang case 0x07:
613ffee1ddeSZhao Qiang case 0x35:
614ffee1ddeSZhao Qiang fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 0);
615ffee1ddeSZhao Qiang fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1);
616ffee1ddeSZhao Qiang break;
617ffee1ddeSZhao Qiang default:
618ffee1ddeSZhao Qiang break;
619ffee1ddeSZhao Qiang }
620ffee1ddeSZhao Qiang }
621ffee1ddeSZhao Qiang
622d31e53b4STimur Tabi /*
623d31e53b4STimur Tabi * For 10G, we only support one XAUI card per Fman. If present, then we
624d31e53b4STimur Tabi * force its routing and never touch those bits again, which removes the
625d31e53b4STimur Tabi * need for Linux to do any muxing. This works because of the way
626d31e53b4STimur Tabi * BRDCFG1 is defined, but it's a bit hackish.
627d31e53b4STimur Tabi *
628d31e53b4STimur Tabi * The PHY address for the XAUI card depends on which slot it's in. The
629d31e53b4STimur Tabi * macros we use imply that the PHY address is based on which FM, but
630d31e53b4STimur Tabi * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
631d31e53b4STimur Tabi * and FM2 could only use a XAUI in slot 4. On the Hydra board, we
632d31e53b4STimur Tabi * check the actual slot and just use the macros as-is, even though
633d31e53b4STimur Tabi * the P3041 and P5020 only have one Fman.
634d31e53b4STimur Tabi */
635d31e53b4STimur Tabi lane = serdes_get_first_lane(XAUI_FM1);
636d31e53b4STimur Tabi if (lane >= 0) {
637d31e53b4STimur Tabi debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]);
638e14cdc0aSShaohui Xie mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK;
639e14cdc0aSShaohui Xie mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT2;
640d31e53b4STimur Tabi super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO",
641d31e53b4STimur Tabi mdio_mux[i].mask, mdio_mux[i].val);
642d31e53b4STimur Tabi }
643d31e53b4STimur Tabi
644d31e53b4STimur Tabi fm_info_set_mdio(FM1_10GEC1,
645d31e53b4STimur Tabi miiphy_get_dev_by_name("SUPER_HYDRA_FM1_TGEC_MDIO"));
646d31e53b4STimur Tabi
647d31e53b4STimur Tabi #if (CONFIG_SYS_NUM_FMAN == 2)
648d31e53b4STimur Tabi for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
649d31e53b4STimur Tabi int idx = i - FM2_DTSEC1;
650d31e53b4STimur Tabi
651d31e53b4STimur Tabi switch (fm_info_get_enet_if(i)) {
652d31e53b4STimur Tabi case PHY_INTERFACE_MODE_SGMII:
653d31e53b4STimur Tabi lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
654d31e53b4STimur Tabi if (lane < 0)
655d31e53b4STimur Tabi break;
656d31e53b4STimur Tabi slot = lane_to_slot[lane];
657d31e53b4STimur Tabi mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
658d31e53b4STimur Tabi debug("FM2@DTSEC%u expects SGMII in slot %u\n",
659d31e53b4STimur Tabi idx + 1, slot);
660d31e53b4STimur Tabi switch (slot) {
661d31e53b4STimur Tabi case 1:
662d31e53b4STimur Tabi mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
663d31e53b4STimur Tabi BRDCFG1_EMI1_EN;
664d31e53b4STimur Tabi break;
665d31e53b4STimur Tabi case 2:
666d31e53b4STimur Tabi mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
667d31e53b4STimur Tabi BRDCFG1_EMI1_EN;
668d31e53b4STimur Tabi break;
669d31e53b4STimur Tabi case 3:
670d31e53b4STimur Tabi mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 |
671d31e53b4STimur Tabi BRDCFG1_EMI1_EN;
672d31e53b4STimur Tabi break;
673d31e53b4STimur Tabi case 5:
674d31e53b4STimur Tabi mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
675d31e53b4STimur Tabi BRDCFG1_EMI1_EN;
676d31e53b4STimur Tabi break;
677d31e53b4STimur Tabi case 6:
678d31e53b4STimur Tabi mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
679d31e53b4STimur Tabi BRDCFG1_EMI1_EN;
680d31e53b4STimur Tabi break;
681d31e53b4STimur Tabi case 7:
682d31e53b4STimur Tabi mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
683d31e53b4STimur Tabi BRDCFG1_EMI1_EN;
684d31e53b4STimur Tabi break;
685d31e53b4STimur Tabi };
686d31e53b4STimur Tabi
687d5689824SZhao Qiang if (i == FM2_DTSEC1 || i == FM2_DTSEC2) {
688d5689824SZhao Qiang super_hydra_mdio_set_mux(
689d5689824SZhao Qiang "SUPER_HYDRA_FM3_SGMII_MDIO",
690d5689824SZhao Qiang mdio_mux[i].mask,
691d5689824SZhao Qiang mdio_mux[i].val);
692d5689824SZhao Qiang fm_info_set_mdio(i, miiphy_get_dev_by_name(
693d5689824SZhao Qiang "SUPER_HYDRA_FM3_SGMII_MDIO"));
694d5689824SZhao Qiang } else {
695d5689824SZhao Qiang super_hydra_mdio_set_mux(
696d5689824SZhao Qiang "SUPER_HYDRA_FM2_SGMII_MDIO",
697d5689824SZhao Qiang mdio_mux[i].mask,
698d5689824SZhao Qiang mdio_mux[i].val);
699d5689824SZhao Qiang fm_info_set_mdio(i, miiphy_get_dev_by_name(
700d5689824SZhao Qiang "SUPER_HYDRA_FM2_SGMII_MDIO"));
701d5689824SZhao Qiang }
702d5689824SZhao Qiang
703d31e53b4STimur Tabi break;
704d31e53b4STimur Tabi case PHY_INTERFACE_MODE_RGMII:
705d31e53b4STimur Tabi /*
706d31e53b4STimur Tabi * FM1 DTSEC5 is routed via EC1 to the first on-board
707d31e53b4STimur Tabi * RGMII port. FM2 DTSEC5 is routed via EC2 to the
708d31e53b4STimur Tabi * second on-board RGMII port. The other DTSECs cannot
709d31e53b4STimur Tabi * be routed to RGMII.
710d31e53b4STimur Tabi */
711d31e53b4STimur Tabi debug("FM2@DTSEC%u is RGMII at address %u\n",
712d31e53b4STimur Tabi idx + 1, 1);
713d31e53b4STimur Tabi fm_info_set_phy_address(i, 1);
714d31e53b4STimur Tabi mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
715d31e53b4STimur Tabi mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
716d31e53b4STimur Tabi BRDCFG1_EMI1_EN;
717d31e53b4STimur Tabi super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO",
718d31e53b4STimur Tabi mdio_mux[i].mask, mdio_mux[i].val);
719d31e53b4STimur Tabi fm_info_set_mdio(i,
720d31e53b4STimur Tabi miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
721d31e53b4STimur Tabi break;
722d31e53b4STimur Tabi case PHY_INTERFACE_MODE_NONE:
723d31e53b4STimur Tabi fm_info_set_phy_address(i, 0);
724d31e53b4STimur Tabi break;
725d31e53b4STimur Tabi default:
726d31e53b4STimur Tabi printf("Fman2: DTSEC%u set to unknown interface %i\n",
727d31e53b4STimur Tabi idx + 1, fm_info_get_enet_if(i));
728d31e53b4STimur Tabi fm_info_set_phy_address(i, 0);
729d31e53b4STimur Tabi break;
730d31e53b4STimur Tabi }
731d31e53b4STimur Tabi }
732d31e53b4STimur Tabi
733ffee1ddeSZhao Qiang bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO");
734ffee1ddeSZhao Qiang set_sgmii_phy(bus, FM2_DTSEC3, PORT_NUM_FM2, PHY_BASE_ADDR);
735ffee1ddeSZhao Qiang bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM3_SGMII_MDIO");
736ffee1ddeSZhao Qiang set_sgmii_phy(bus, FM2_DTSEC1, PORT_NUM_FM2, PHY_BASE_ADDR);
737ffee1ddeSZhao Qiang
738d31e53b4STimur Tabi /*
739d31e53b4STimur Tabi * For 10G, we only support one XAUI card per Fman. If present, then we
740d31e53b4STimur Tabi * force its routing and never touch those bits again, which removes the
741d31e53b4STimur Tabi * need for Linux to do any muxing. This works because of the way
742d31e53b4STimur Tabi * BRDCFG1 is defined, but it's a bit hackish.
743d31e53b4STimur Tabi *
744d31e53b4STimur Tabi * The PHY address for the XAUI card depends on which slot it's in. The
745d31e53b4STimur Tabi * macros we use imply that the PHY address is based on which FM, but
746d31e53b4STimur Tabi * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
747d31e53b4STimur Tabi * and FM2 could only use a XAUI in slot 4. On the Hydra board, we
748d31e53b4STimur Tabi * check the actual slot and just use the macros as-is, even though
749d31e53b4STimur Tabi * the P3041 and P5020 only have one Fman.
750d31e53b4STimur Tabi */
751d31e53b4STimur Tabi lane = serdes_get_first_lane(XAUI_FM2);
752d31e53b4STimur Tabi if (lane >= 0) {
753d31e53b4STimur Tabi debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]);
754e14cdc0aSShaohui Xie mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK;
755e14cdc0aSShaohui Xie mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT1;
756d31e53b4STimur Tabi super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO",
757d31e53b4STimur Tabi mdio_mux[i].mask, mdio_mux[i].val);
758d31e53b4STimur Tabi }
759d31e53b4STimur Tabi
760d31e53b4STimur Tabi fm_info_set_mdio(FM2_10GEC1,
761d31e53b4STimur Tabi miiphy_get_dev_by_name("SUPER_HYDRA_FM2_TGEC_MDIO"));
762d31e53b4STimur Tabi
763d31e53b4STimur Tabi #endif
764d31e53b4STimur Tabi
765d31e53b4STimur Tabi cpu_eth_init(bis);
766d31e53b4STimur Tabi #endif
767d31e53b4STimur Tabi
768d31e53b4STimur Tabi return pci_eth_init(bis);
769d31e53b4STimur Tabi }
770