183d290c5STom Rini// SPDX-License-Identifier: GPL-2.0 294a66604SRabeeh Khoury/* 394a66604SRabeeh Khoury * Copyright (C) 2016 Marvell International Ltd. 494a66604SRabeeh Khoury */ 594a66604SRabeeh Khoury 694a66604SRabeeh Khoury#include "armada-8040.dtsi" /* include SoC device tree */ 794a66604SRabeeh Khoury 894a66604SRabeeh Khoury/ { 994a66604SRabeeh Khoury model = "MACCHIATOBin-8040"; 1094a66604SRabeeh Khoury compatible = "marvell,armada8040-mcbin", 1194a66604SRabeeh Khoury "marvell,armada8040"; 1294a66604SRabeeh Khoury 1394a66604SRabeeh Khoury chosen { 1494a66604SRabeeh Khoury stdout-path = "serial0:115200n8"; 1594a66604SRabeeh Khoury }; 1694a66604SRabeeh Khoury 1794a66604SRabeeh Khoury aliases { 1894a66604SRabeeh Khoury i2c0 = &cpm_i2c0; 1994a66604SRabeeh Khoury i2c1 = &cpm_i2c1; 2094a66604SRabeeh Khoury spi0 = &cps_spi1; 2194a66604SRabeeh Khoury gpio0 = &ap_gpio0; 2294a66604SRabeeh Khoury gpio1 = &cpm_gpio0; 2394a66604SRabeeh Khoury gpio2 = &cpm_gpio1; 2494a66604SRabeeh Khoury }; 2594a66604SRabeeh Khoury 2694a66604SRabeeh Khoury memory@00000000 { 2794a66604SRabeeh Khoury device_type = "memory"; 2894a66604SRabeeh Khoury reg = <0x0 0x0 0x0 0x80000000>; 2994a66604SRabeeh Khoury }; 3094a66604SRabeeh Khoury 3194a66604SRabeeh Khoury simple-bus { 3294a66604SRabeeh Khoury compatible = "simple-bus"; 3394a66604SRabeeh Khoury #address-cells = <1>; 3494a66604SRabeeh Khoury #size-cells = <0>; 3594a66604SRabeeh Khoury 3694a66604SRabeeh Khoury reg_usb3h0_vbus: usb3-vbus0 { 3794a66604SRabeeh Khoury compatible = "regulator-fixed"; 3894a66604SRabeeh Khoury pinctrl-names = "default"; 3994a66604SRabeeh Khoury pinctrl-0 = <&cpm_xhci_vbus_pins>; 4094a66604SRabeeh Khoury regulator-name = "reg-usb3h0-vbus"; 4194a66604SRabeeh Khoury regulator-min-microvolt = <5000000>; 4294a66604SRabeeh Khoury regulator-max-microvolt = <5000000>; 4394a66604SRabeeh Khoury startup-delay-us = <500000>; 4494a66604SRabeeh Khoury enable-active-high; 4594a66604SRabeeh Khoury regulator-always-on; 4694a66604SRabeeh Khoury regulator-boot-on; 4794a66604SRabeeh Khoury gpio = <&cpm_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */ 4894a66604SRabeeh Khoury }; 4994a66604SRabeeh Khoury }; 5094a66604SRabeeh Khoury}; 5194a66604SRabeeh Khoury 5294a66604SRabeeh Khoury/* Accessible over the mini-USB CON9 connector on the main board */ 5394a66604SRabeeh Khoury&uart0 { 5494a66604SRabeeh Khoury status = "okay"; 5594a66604SRabeeh Khoury}; 5694a66604SRabeeh Khoury 5794a66604SRabeeh Khoury&ap_pinctl { 5894a66604SRabeeh Khoury /* 5994a66604SRabeeh Khoury * MPP Bus: 6094a66604SRabeeh Khoury * eMMC [0-10] 6194a66604SRabeeh Khoury * UART0 [11,19] 6294a66604SRabeeh Khoury */ 6394a66604SRabeeh Khoury /* 0 1 2 3 4 5 6 7 8 9 */ 6494a66604SRabeeh Khoury pin-func = < 1 1 1 1 1 1 1 1 1 1 6594a66604SRabeeh Khoury 1 3 0 0 0 0 0 0 0 3 >; 6694a66604SRabeeh Khoury}; 6794a66604SRabeeh Khoury 6894a66604SRabeeh Khoury/* on-board eMMC */ 6994a66604SRabeeh Khoury&ap_sdhci0 { 7094a66604SRabeeh Khoury pinctrl-names = "default"; 7194a66604SRabeeh Khoury pinctrl-0 = <&ap_emmc_pins>; 7294a66604SRabeeh Khoury bus-width= <8>; 7394a66604SRabeeh Khoury status = "okay"; 7494a66604SRabeeh Khoury}; 7594a66604SRabeeh Khoury 7694a66604SRabeeh Khoury&cpm_pinctl { 7794a66604SRabeeh Khoury /* 7894a66604SRabeeh Khoury * MPP Bus: 7994a66604SRabeeh Khoury * [0-31] = 0xff: Keep default CP0_shared_pins: 8094a66604SRabeeh Khoury * [11] CLKOUT_MPP_11 (out) 8194a66604SRabeeh Khoury * [23] LINK_RD_IN_CP2CP (in) 8294a66604SRabeeh Khoury * [25] CLKOUT_MPP_25 (out) 8394a66604SRabeeh Khoury * [29] AVS_FB_IN_CP2CP (in) 8494a66604SRabeeh Khoury * [32,34] SMI 8594a66604SRabeeh Khoury * [33] MSS power down 8694a66604SRabeeh Khoury * [35-38] CP0 I2C1 and I2C0 8794a66604SRabeeh Khoury * [39] MSS CKE Enable 8894a66604SRabeeh Khoury * [40,41] CP0 UART1 TX/RX 8994a66604SRabeeh Khoury * [42,43] XSMI (controls two 10G phys) 9094a66604SRabeeh Khoury * [47] USB VBUS EN 9194a66604SRabeeh Khoury * [48] FAN PWM 9294a66604SRabeeh Khoury * [49] 10G port 1 interrupt 9394a66604SRabeeh Khoury * [50] 10G port 0 interrupt 9494a66604SRabeeh Khoury * [51] 2.5G SFP TX fault 9594a66604SRabeeh Khoury * [52] PCIe reset out 9694a66604SRabeeh Khoury * [53] 2.5G SFP mode 9794a66604SRabeeh Khoury * [54] 2.5G SFP LOS 9894a66604SRabeeh Khoury * [55] Micro SD card detect 9994a66604SRabeeh Khoury * [56-61] Micro SD 100cb686454SStefan Roese * [62] CP1 SFI SFP FAULT 10194a66604SRabeeh Khoury */ 10294a66604SRabeeh Khoury /* 0 1 2 3 4 5 6 7 8 9 */ 10394a66604SRabeeh Khoury pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 10494a66604SRabeeh Khoury 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 10594a66604SRabeeh Khoury 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 10694a66604SRabeeh Khoury 0xff 0 7 0xa 7 2 2 2 2 0xa 10794a66604SRabeeh Khoury 7 7 8 8 0 0 0 0 0 0 10894a66604SRabeeh Khoury 0 0 0 0 0 0 0xe 0xe 0xe 0xe 10994a66604SRabeeh Khoury 0xe 0xe 0 >; 11094a66604SRabeeh Khoury 11194a66604SRabeeh Khoury cpm_xhci_vbus_pins: cpm-xhci-vbus-pins { 11294a66604SRabeeh Khoury marvell,pins = < 47 >; 11394a66604SRabeeh Khoury marvell,function = <0>; 11494a66604SRabeeh Khoury }; 11594a66604SRabeeh Khoury 11694a66604SRabeeh Khoury cpm_pcie_reset_pins: cpm-pcie-reset-pins { 11794a66604SRabeeh Khoury marvell,pins = < 52 >; 11894a66604SRabeeh Khoury marvell,function = <0>; 11994a66604SRabeeh Khoury }; 12094a66604SRabeeh Khoury}; 12194a66604SRabeeh Khoury 12294a66604SRabeeh Khoury/* uSD slot */ 12394a66604SRabeeh Khoury&cpm_sdhci0 { 12494a66604SRabeeh Khoury pinctrl-names = "default"; 12594a66604SRabeeh Khoury pinctrl-0 = <&cpm_sdhci_pins>; 12694a66604SRabeeh Khoury bus-width= <4>; 12794a66604SRabeeh Khoury status = "okay"; 12894a66604SRabeeh Khoury}; 12994a66604SRabeeh Khoury 13094a66604SRabeeh Khoury/* PCIe x4 */ 13194a66604SRabeeh Khoury&cpm_pcie0 { 13294a66604SRabeeh Khoury num-lanes = <4>; 13394a66604SRabeeh Khoury pinctrl-names = "default"; 13494a66604SRabeeh Khoury pinctrl-0 = <&cpm_pcie_reset_pins>; 135*f301ba55SBaruch Siach marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */ 13694a66604SRabeeh Khoury status = "okay"; 13794a66604SRabeeh Khoury}; 13894a66604SRabeeh Khoury 13994a66604SRabeeh Khoury&cpm_i2c0 { 14094a66604SRabeeh Khoury pinctrl-names = "default"; 14194a66604SRabeeh Khoury pinctrl-0 = <&cpm_i2c0_pins>; 14294a66604SRabeeh Khoury status = "okay"; 14394a66604SRabeeh Khoury clock-frequency = <100000>; 14494a66604SRabeeh Khoury}; 14594a66604SRabeeh Khoury 14694a66604SRabeeh Khoury&cpm_i2c1 { 14794a66604SRabeeh Khoury pinctrl-names = "default"; 14894a66604SRabeeh Khoury pinctrl-0 = <&cpm_i2c1_pins>; 14994a66604SRabeeh Khoury status = "okay"; 15094a66604SRabeeh Khoury clock-frequency = <100000>; 15194a66604SRabeeh Khoury}; 15294a66604SRabeeh Khoury 15394a66604SRabeeh Khoury&cpm_sata0 { 15494a66604SRabeeh Khoury status = "okay"; 15594a66604SRabeeh Khoury}; 15694a66604SRabeeh Khoury 157eff26e48SBaruch Siach&cpm_mdio { 158eff26e48SBaruch Siach ge_phy: ethernet-phy@0 { 159eff26e48SBaruch Siach reg = <0>; 160eff26e48SBaruch Siach }; 161eff26e48SBaruch Siach}; 162eff26e48SBaruch Siach 16394a66604SRabeeh Khoury&cpm_comphy { 16494a66604SRabeeh Khoury /* 16594a66604SRabeeh Khoury * CP0 Serdes Configuration: 16694a66604SRabeeh Khoury * Lane 0: PCIe0 (x4) 16794a66604SRabeeh Khoury * Lane 1: PCIe0 (x4) 16894a66604SRabeeh Khoury * Lane 2: PCIe0 (x4) 16994a66604SRabeeh Khoury * Lane 3: PCIe0 (x4) 170cb686454SStefan Roese * Lane 4: SFI (10G) 17194a66604SRabeeh Khoury * Lane 5: SATA1 17294a66604SRabeeh Khoury */ 17394a66604SRabeeh Khoury phy0 { 17494a66604SRabeeh Khoury phy-type = <PHY_TYPE_PEX0>; 17594a66604SRabeeh Khoury }; 17694a66604SRabeeh Khoury phy1 { 17794a66604SRabeeh Khoury phy-type = <PHY_TYPE_PEX0>; 17894a66604SRabeeh Khoury }; 17994a66604SRabeeh Khoury phy2 { 18094a66604SRabeeh Khoury phy-type = <PHY_TYPE_PEX0>; 18194a66604SRabeeh Khoury }; 18294a66604SRabeeh Khoury phy3 { 18394a66604SRabeeh Khoury phy-type = <PHY_TYPE_PEX0>; 18494a66604SRabeeh Khoury }; 18594a66604SRabeeh Khoury phy4 { 186cb686454SStefan Roese phy-type = <PHY_TYPE_SFI>; 18794a66604SRabeeh Khoury }; 18894a66604SRabeeh Khoury phy5 { 18994a66604SRabeeh Khoury phy-type = <PHY_TYPE_SATA1>; 19094a66604SRabeeh Khoury }; 19194a66604SRabeeh Khoury}; 19294a66604SRabeeh Khoury 19394a66604SRabeeh Khoury&cps_sata0 { 19494a66604SRabeeh Khoury status = "okay"; 19594a66604SRabeeh Khoury}; 19694a66604SRabeeh Khoury 19794a66604SRabeeh Khoury&cps_usb3_0 { 19894a66604SRabeeh Khoury vbus-supply = <®_usb3h0_vbus>; 19994a66604SRabeeh Khoury status = "okay"; 20094a66604SRabeeh Khoury}; 20194a66604SRabeeh Khoury 20294a66604SRabeeh Khoury&cps_utmi0 { 20394a66604SRabeeh Khoury status = "okay"; 20494a66604SRabeeh Khoury}; 20594a66604SRabeeh Khoury 206eff26e48SBaruch Siach&cps_ethernet { 207eff26e48SBaruch Siach status = "okay"; 208eff26e48SBaruch Siach}; 209eff26e48SBaruch Siach 210eff26e48SBaruch Siach&cps_eth1 { 211eff26e48SBaruch Siach status = "okay"; 212eff26e48SBaruch Siach phy = <&ge_phy>; 213eff26e48SBaruch Siach phy-mode = "sgmii"; 214eff26e48SBaruch Siach}; 215eff26e48SBaruch Siach 21694a66604SRabeeh Khoury&cps_pinctl { 21794a66604SRabeeh Khoury /* 21894a66604SRabeeh Khoury * MPP Bus: 21994a66604SRabeeh Khoury * [0-5] TDM 22094a66604SRabeeh Khoury * [6,7] CP1_UART 0 22194a66604SRabeeh Khoury * [8] CP1 10G SFP LOS 22294a66604SRabeeh Khoury * [9] CP1 10G PHY RESET 22394a66604SRabeeh Khoury * [10] CP1 10G SFP TX Disable 22494a66604SRabeeh Khoury * [11] CP1 10G SFP Mode 22594a66604SRabeeh Khoury * [12] SPI1 CS1n 22694a66604SRabeeh Khoury * [13] SPI1 MISO (TDM and SPI ROM shared) 22794a66604SRabeeh Khoury * [14] SPI1 CS0n 22894a66604SRabeeh Khoury * [15] SPI1 MOSI (TDM and SPI ROM shared) 22994a66604SRabeeh Khoury * [16] SPI1 CLK (TDM and SPI ROM shared) 23094a66604SRabeeh Khoury * [24] CP1 2.5G SFP TX Disable 23194a66604SRabeeh Khoury * [26] CP0 10G SFP TX Fault 23294a66604SRabeeh Khoury * [27] CP0 10G SFP Mode 23394a66604SRabeeh Khoury * [28] CP0 10G SFP LOS 23494a66604SRabeeh Khoury * [29] CP0 10G SFP TX Disable 23594a66604SRabeeh Khoury * [30] USB Over current indication 23694a66604SRabeeh Khoury * [31] 10G Port 0 phy reset 23794a66604SRabeeh Khoury * [32-62] = 0xff: Keep default CP1_shared_pins: 23894a66604SRabeeh Khoury */ 23994a66604SRabeeh Khoury /* 0 1 2 3 4 5 6 7 8 9 */ 24094a66604SRabeeh Khoury pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x8 0x8 0x0 0x0 24194a66604SRabeeh Khoury 0x0 0x0 0x3 0x3 0x3 0x3 0x3 0xff 0xff 0xff 24294a66604SRabeeh Khoury 0xff 0xff 0xff 0xff 0x0 0xff 0x0 0x0 0x0 0x0 24394a66604SRabeeh Khoury 0x0 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 24494a66604SRabeeh Khoury 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 24594a66604SRabeeh Khoury 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 24694a66604SRabeeh Khoury 0xff 0xff 0xff>; 24794a66604SRabeeh Khoury}; 24894a66604SRabeeh Khoury 24994a66604SRabeeh Khoury&cps_spi1 { 25094a66604SRabeeh Khoury pinctrl-names = "default"; 25194a66604SRabeeh Khoury pinctrl-0 = <&cps_spi1_pins>; 25294a66604SRabeeh Khoury status = "okay"; 25394a66604SRabeeh Khoury 25494a66604SRabeeh Khoury spi-flash@0 { 25594a66604SRabeeh Khoury #address-cells = <1>; 25694a66604SRabeeh Khoury #size-cells = <1>; 25794a66604SRabeeh Khoury compatible = "jedec,spi-nor"; 25894a66604SRabeeh Khoury reg = <0>; 25994a66604SRabeeh Khoury spi-max-frequency = <10000000>; 26094a66604SRabeeh Khoury 26194a66604SRabeeh Khoury partitions { 26294a66604SRabeeh Khoury compatible = "fixed-partitions"; 26394a66604SRabeeh Khoury #address-cells = <1>; 26494a66604SRabeeh Khoury #size-cells = <1>; 26594a66604SRabeeh Khoury 26694a66604SRabeeh Khoury partition@0 { 26794a66604SRabeeh Khoury label = "U-Boot"; 26894a66604SRabeeh Khoury reg = <0 0x200000>; 26994a66604SRabeeh Khoury }; 27094a66604SRabeeh Khoury partition@400000 { 27194a66604SRabeeh Khoury label = "Filesystem"; 27294a66604SRabeeh Khoury reg = <0x200000 0xce0000>; 27394a66604SRabeeh Khoury }; 27494a66604SRabeeh Khoury }; 27594a66604SRabeeh Khoury }; 27694a66604SRabeeh Khoury}; 27794a66604SRabeeh Khoury 27894a66604SRabeeh Khoury&cps_comphy { 27994a66604SRabeeh Khoury /* 28094a66604SRabeeh Khoury * CP1 Serdes Configuration: 281fdc9e880SStefan Roese * Lane 0: SGMII1 28294a66604SRabeeh Khoury * Lane 1: SATA 0 28394a66604SRabeeh Khoury * Lane 2: USB HOST 0 28494a66604SRabeeh Khoury * Lane 3: SATA1 285cb686454SStefan Roese * Lane 4: SFI (10G) 28694a66604SRabeeh Khoury * Lane 5: SGMII3 28794a66604SRabeeh Khoury */ 28894a66604SRabeeh Khoury phy0 { 289fdc9e880SStefan Roese phy-type = <PHY_TYPE_SGMII1>; 29094a66604SRabeeh Khoury phy-speed = <PHY_SPEED_1_25G>; 29194a66604SRabeeh Khoury }; 29294a66604SRabeeh Khoury phy1 { 29394a66604SRabeeh Khoury phy-type = <PHY_TYPE_SATA0>; 29494a66604SRabeeh Khoury }; 29594a66604SRabeeh Khoury phy2 { 29694a66604SRabeeh Khoury phy-type = <PHY_TYPE_USB3_HOST0>; 29794a66604SRabeeh Khoury }; 29894a66604SRabeeh Khoury phy3 { 29994a66604SRabeeh Khoury phy-type = <PHY_TYPE_SATA1>; 30094a66604SRabeeh Khoury }; 30194a66604SRabeeh Khoury phy4 { 302cb686454SStefan Roese phy-type = <PHY_TYPE_SFI>; 30394a66604SRabeeh Khoury }; 30494a66604SRabeeh Khoury phy5 { 30594a66604SRabeeh Khoury phy-type = <PHY_TYPE_SGMII3>; 30694a66604SRabeeh Khoury }; 30794a66604SRabeeh Khoury}; 308