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/openbmc/linux/arch/x86/kernel/
H A Dtsc_msr.c22 * The frequency numbers in the SDM are e.g. 83.3 MHz, which does not contain a
24 * use a 25 MHz crystal and Cherry Trail uses a 19.2 MHz crystal, the crystal
25 * is the source clk for a root PLL which outputs 1600 and 100 MHz. It is
31 * clock of 100 MHz plus a quotient which gets us as close to the frequency
33 * For the 83.3 MHz example from above this would give us 100 MHz * 5 / 6 =
34 * 83 and 1/3 MHz, which matches exactly what has been measured on actual hw.
80 * 000: 100 * 5 / 6 = 83.3333 MHz
81 * 001: 100 * 1 / 1 = 100.0000 MHz
82 * 010: 100 * 4 / 3 = 133.3333 MHz
83 * 011: 100 * 7 / 6 = 116.6667 MHz
[all …]
/openbmc/u-boot/board/freescale/common/
H A Didt8t49n222a_serdes_clk.c64 debug("Only one refclk at 122.88MHz is not supported." in set_serdes_refclk()
65 " Please set both refclk1 & refclk2 to 122.88MHz" in set_serdes_refclk()
66 " or both not to 122.88MHz.\n"); in set_serdes_refclk()
73 debug("refclk1 should be 100MHZ, 122.88MHz, 125MHz" in set_serdes_refclk()
74 " or 156.25MHz.\n"); in set_serdes_refclk()
81 debug("refclk2 should be 100MHZ, 122.88MHz, 125MHz" in set_serdes_refclk()
82 " or 156.25MHz.\n"); in set_serdes_refclk()
92 * Refclk1 = 122.88MHz Refclk2 = 122.88MHz in set_serdes_refclk()
117 * Refclk1 = 100MHz Refclk2 = 125MHz in set_serdes_refclk()
120 printf("Setting refclk1:100 and refclk2:125\n"); in set_serdes_refclk()
[all …]
H A Didt8t49n222a_serdes_clk.h22 SERDES_REFCLK_100, /* refclk 100Mhz */
23 SERDES_REFCLK_122_88, /* refclk 122.88Mhz */
24 SERDES_REFCLK_125, /* refclk 125Mhz */
25 SERDES_REFCLK_156_25, /* refclk 156.25Mhz */
30 * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
42 * Refclk1 not equal to 122.88MHz Refclk2 not equal to 122.88MHz
54 * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
63 * Refclk1 : 156.25MHz Refclk2 : 156.25MHz
71 * Refclk1 : 100MHz Refclk2 : 156.25MHz
79 * Refclk1 : 125MHz Refclk2 : 156.25MHz
[all …]
/openbmc/u-boot/board/freescale/bsc9132qds/
H A DREADME23 ECC), up to 1333 MHz data rate
73 Core MHz/CCB MHz/DDR(MT/s)
74 1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz
75 (SYSCLK = 100MHz, DDRCLK = 100MHz)
76 2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz
77 (SYSCLK = 100MHz, DDRCLK = 133MHz)
94 make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK
95 make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK
98 make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK
99 make BSC9132QDS_SPIFLASH_DDRCLK133 : For 133MHZ DDR CLK
[all …]
/openbmc/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
94 mode "640x480-100"
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
[all …]
/openbmc/u-boot/drivers/mmc/
H A Dbcmstb_sdhci.c15 * capability is 100 MHz. The divisor that is eventually written to
19 * This define used to be set to 52000000 (52 MHz), the desired
21 * actually running at 100 MHz (seemingly without issue), which is
24 * Now, by setting this to 0 (auto-detect), 100 MHz will be read from
27 * in-spec 52 MHz value.
32 * sets it to 100 MHz divided by SDHCI_MAX_DIV_SPEC_300, or 48,875 Hz,
/openbmc/u-boot/board/samsung/odroid/
H A Dodroid.c126 /* Set APLL to 1000MHz */ in board_clock_init()
149 * Set dividers for MOUTcore = 1000 MHz in board_clock_init()
150 * coreout = MOUT / (ratio + 1) = 1000 MHz (0) in board_clock_init()
151 * corem0 = armclk / (ratio + 1) = 333 MHz (2) in board_clock_init()
152 * corem1 = armclk / (ratio + 1) = 166 MHz (5) in board_clock_init()
153 * periph = armclk / (ratio + 1) = 1000 MHz (0) in board_clock_init()
154 * atbout = MOUT / (ratio + 1) = 200 MHz (4) in board_clock_init()
155 * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1) in board_clock_init()
156 * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0) in board_clock_init()
157 * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk) in board_clock_init()
[all …]
/openbmc/linux/drivers/media/i2c/et8ek8/
H A Det8ek8_mode.c20 * SPCK = 80 MHz
21 * CCP2 = 640 MHz
22 * VCO = 640 MHz
49 .numerator = 100,
121 * SPCK = 80 MHz
122 * CCP2 = 560 MHz
123 * VCO = 560 MHz
150 .numerator = 100,
177 * SPCK = 96.5333333333333 MHz
178 * CCP2 = 579.2 MHz
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A Dclock_am33xx.c67 { /* 19.2 MHz */
70 {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
75 { /* 24 MHz */
78 {25, 0, 1, -1, -1, -1, -1}, /* OPP 100 */
80 {100, 3, 1, -1, -1, -1, -1}, /* OPP TB */
83 { /* 25 MHz */
86 {24, 0, 1, -1, -1, -1, -1}, /* OPP 100 */
91 { /* 26 MHz */
94 {300, 12, 1, -1, -1, -1, -1}, /* OPP 100 */
102 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
[all …]
/openbmc/linux/drivers/cpufreq/
H A Ds5pv210-cpufreq.c87 /* APLL M,P,S values for 1G/800Mhz */
89 #define APLL_VAL_800 ((1 << 31) | (100 << 16) | (3 << 8) | 1)
91 /* Use 800MHz when entering sleep mode */
129 {0, L4, 100*1000},
175 /* L0 : [1000/200/100][166/83][133/66][200/200] */
178 /* L1 : [800/200/100][166/83][133/66][200/200] */
181 /* L2 : [400/200/100][166/83][133/66][200/200] */
184 /* L3 : [200/200/100][166/83][133/66][200/200] */
187 /* L4 : [100/100/100][83/83][66/66][100/100] */
275 * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287 in s5pv210_target()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3399.h69 #define MHz 1000000 macro
71 #define OSC_HZ (24*MHz)
72 #define LPLL_HZ (600*MHz)
73 #define BPLL_HZ (600*MHz)
74 #define GPLL_HZ (594*MHz)
75 #define CPLL_HZ (384*MHz)
76 #define PPLL_HZ (676*MHz)
78 #define PMU_PCLK_HZ (48*MHz)
80 #define ACLKM_CORE_L_HZ (300*MHz)
81 #define ATCLK_CORE_L_HZ (300*MHz)
[all …]
/openbmc/linux/tools/testing/selftests/intel_pstate/
H A Drun.sh6 # state to the minimum supported frequency, in decrements of 100MHz. The
10 # or the requested frequency in MHz, the Actual frequency, as read from
22 #/tmp/result.3100:1:cpu MHz : 2899.980
23 #/tmp/result.3100:2:cpu MHz : 2900.000
28 # for consistency and modified to remove the extra MHz values. The result.X
60 grep MHz /proc/cpuinfo | sort -u > /tmp/result.freqs
80 # MAIN (ALL UNITS IN MHZ)
95 [ $EVALUATE_ONLY -eq 0 ] && for freq in `seq $max_freq -100 $min_freq`
98 cpupower frequency-set -g powersave --max=${freq}MHz >& /dev/null
102 [ $EVALUATE_ONLY -eq 0 ] && cpupower frequency-set -g powersave --max=${max_freq}MHz >& /dev/null
[all …]
/openbmc/u-boot/board/freescale/t102xqds/
H A DREADME100 - Two on-board RGMII 10M/100M/1G ethernet ports.
114 - Switch selectable to one of 16 common settings in the interval of 64 MHz-166 MHz.
115 - Software programmable in 1 MHz increments from 1-200 MHz.
118 - 100 MHz, 125 MHz and 156.25 MHz options.
119 - Spread-spectrum option for 100 MHz.
196 0x6F 100MHz 125MHz 1101
197 0xD6 100MHz 100MHz 1111
198 0x99 156.25MHz 100MHz 1011
204 Bin1: 1400MHz 1600MT/s 400MHz 700MHz
205 Bin2: 1200MHz 1600MT/s 400MHz 600MHz
[all …]
H A Dt1024_sd_rcw.cfg1 # single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
2 # Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
H A Dt1024_nand_rcw.cfg1 # single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
2 # Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
/openbmc/u-boot/drivers/i2c/
H A Daspeed_i2c_global.c27 * APB clk : 100Mhz
30 * I2CG10[23:16] base clk3 for Standard-mode (100Khz) min tBuf 4.7us
31 * 0x3c : 100.8Khz : 3.225Mhz : 4.96us
32 * 0x3d : 99.2Khz : 3.174Mhz : 5.04us
33 * 0x3e : 97.65Khz : 3.125Mhz : 5.12us
34 * 0x40 : 97.75Khz : 3.03Mhz : 5.28us
35 * 0x41 : 99.5Khz : 2.98Mhz : 5.36us (default)
37 * 0x12 : 400Khz : 10Mhz : 1.6us
38 * I2CG10[7:0] base clk1 for Fast-mode Plus (1Mhz) min tBuf 0.5us
39 * 0x08 : 1Mhz : 20Mhz : 0.8us
/openbmc/u-boot/arch/arm/mach-imx/imx8m/
H A Dclock.c352 * LCDIF_PIXEL_CLK: select 800MHz root clock, in mxs_set_lcdclk()
353 * select pre divider 8, output is 100 MHz in mxs_set_lcdclk()
383 /* 500MHz */ in init_usb_clk()
386 /* 100MHz */ in init_usb_clk()
389 /* 100MHz */ in init_usb_clk()
464 * sys pll1 100M in set_clk_qspi()
498 /* set enet axi clock 266Mhz */ in set_clk_enet()
529 DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
531 DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
533 DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
[all …]
/openbmc/u-boot/drivers/video/exynos/
H A Dexynos_mipi_dsi_common.c17 #define MHZ (1000 * 1000) macro
18 #define FIN_HZ (24 * MHZ)
20 #define DFIN_PLL_MIN_HZ (6 * MHZ)
21 #define DFIN_PLL_MAX_HZ (12 * MHZ)
23 #define DFVCO_MIN_HZ (500 * MHZ)
24 #define DFVCO_MAX_HZ (1000 * MHZ)
46 100, 120, 170, 220, 270,
109 delay_val = MHZ / dsim->dsim_config->esc_clk; in exynos_mipi_dsi_wr_data()
267 * ~ 99.99 MHz 0000 in exynos_mipi_dsi_change_pll()
268 * 100 ~ 119.99 MHz 0001 in exynos_mipi_dsi_change_pll()
[all …]
/openbmc/linux/drivers/clk/spear/
H A Dspear1340_clock.c164 /* PCLK 24MHz */
165 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
166 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
167 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
168 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
169 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
170 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
172 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
177 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
178 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
[all …]
/openbmc/linux/arch/mips/jazz/
H A DKconfig7 This is a machine with a R4400 133/150 MHz CPU. To compile a Linux
18 This is a machine with a R4000 100 MHz CPU. To compile a Linux
28 This is a machine with a R4000 100 MHz CPU. To compile a Linux
/openbmc/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-eth.c38 #define PLL_MAX_RETRY 100
61 udelay(100); in clk_eth_enable()
79 /* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */ in clk_eth_enable()
92 udelay(100); in clk_eth_enable()
106 /* switch Esub AXI clock to 208MHz */ in clk_eth_enable()
123 udelay(100); in clk_eth_enable()
/openbmc/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-eth.c38 #define PLL_MAX_RETRY 100
61 udelay(100); in clk_eth_enable()
79 /* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */ in clk_eth_enable()
92 udelay(100); in clk_eth_enable()
106 /* switch Esub AXI clock to 208MHz */ in clk_eth_enable()
123 udelay(100); in clk_eth_enable()
/openbmc/linux/drivers/media/pci/mantis/
H A Dmantis_vp3030.c33 .frequency_min = 47 * MHz,
34 .frequency_max = 862 * MHz,
36 .ref_multiplier = 6, /* 1/6 MHz */
37 .ref_divider = 100000, /* 1/6 MHz */
51 msleep(100); in vp3030_frontend_init()
53 msleep(100); in vp3030_frontend_init()
/openbmc/u-boot/board/freescale/t4rdb/
H A Dt4240rdb.c44 printf(" SERDES1=100MHz SERDES2=156.25MHz\n" in checkboard()
45 " SERDES3=100MHz SERDES4=100MHz\n"); in checkboard()
/openbmc/linux/arch/powerpc/boot/dts/
H A Diss4xx-mpic.dts38 clock-frequency = <100000000>; // 100Mhz :-)
52 clock-frequency = <100000000>; // 100Mhz :-)
68 clock-frequency = <100000000>; // 100Mhz :-)
84 clock-frequency = <100000000>; // 100Mhz :-)

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