17 #define MHZ			(1000 * 1000)  macro
18 #define FIN_HZ			(24 * MHZ)
20 #define DFIN_PLL_MIN_HZ		(6 * MHZ)
21 #define DFIN_PLL_MAX_HZ		(12 * MHZ)
23 #define DFVCO_MIN_HZ		(500 * MHZ)
24 #define DFVCO_MAX_HZ		(1000 * MHZ)
46 	100, 120, 170, 220, 270,
109 	delay_val = MHZ / dsim->dsim_config->esc_clk;  in exynos_mipi_dsi_wr_data()
267 	 *	~ 99.99 MHz			0000  in exynos_mipi_dsi_change_pll()
268 	 *	100 ~ 119.99 MHz		0001  in exynos_mipi_dsi_change_pll()
269 	 *	120 ~ 159.99 MHz		0010  in exynos_mipi_dsi_change_pll()
270 	 *	160 ~ 199.99 MHz		0011  in exynos_mipi_dsi_change_pll()
271 	 *	200 ~ 239.99 MHz		0100  in exynos_mipi_dsi_change_pll()
272 	 *	140 ~ 319.99 MHz		0101  in exynos_mipi_dsi_change_pll()
273 	 *	320 ~ 389.99 MHz		0110  in exynos_mipi_dsi_change_pll()
274 	 *	390 ~ 449.99 MHz		0111  in exynos_mipi_dsi_change_pll()
275 	 *	450 ~ 509.99 MHz		1000  in exynos_mipi_dsi_change_pll()
276 	 *	510 ~ 559.99 MHz		1001  in exynos_mipi_dsi_change_pll()
277 	 *	560 ~ 639.99 MHz		1010  in exynos_mipi_dsi_change_pll()
278 	 *	640 ~ 689.99 MHz		1011  in exynos_mipi_dsi_change_pll()
279 	 *	690 ~ 769.99 MHz		1100  in exynos_mipi_dsi_change_pll()
280 	 *	770 ~ 869.99 MHz		1101  in exynos_mipi_dsi_change_pll()
281 	 *	870 ~ 949.99 MHz		1110  in exynos_mipi_dsi_change_pll()
282 	 *	950 ~ 1000 MHz			1111  in exynos_mipi_dsi_change_pll()
285 		debug("fin_pll range should be 6MHz ~ 12MHz\n");  in exynos_mipi_dsi_change_pll()
288 		if (dfin_pll < 7 * MHZ)  in exynos_mipi_dsi_change_pll()
290 		else if (dfin_pll < 8 * MHZ)  in exynos_mipi_dsi_change_pll()
292 		else if (dfin_pll < 9 * MHZ)  in exynos_mipi_dsi_change_pll()
294 		else if (dfin_pll < 10 * MHZ)  in exynos_mipi_dsi_change_pll()
296 		else if (dfin_pll < 11 * MHZ)  in exynos_mipi_dsi_change_pll()
306 		debug("fvco range should be 500MHz ~ 1000MHz\n");  in exynos_mipi_dsi_change_pll()
313 		if (dpll_out < dpll_table[i] * MHZ) {  in exynos_mipi_dsi_change_pll()
335 		(dpll_out / MHZ));  in exynos_mipi_dsi_change_pll()
376 		if ((byte_clk / esc_div) >= (20 * MHZ) ||  in exynos_mipi_dsi_set_clock()
394 			(byte_clk / MHZ));  in exynos_mipi_dsi_set_clock()
396 			(dsim->dsim_config->esc_clk / MHZ));  in exynos_mipi_dsi_set_clock()
399 			((byte_clk / esc_div) / MHZ));  in exynos_mipi_dsi_set_clock()
405 				(esc_clk_error_rate / 100));  in exynos_mipi_dsi_set_clock()
410 				(esc_clk_error_rate / 100));  in exynos_mipi_dsi_set_clock()
520 	unsigned int time_out = 100;  in exynos_mipi_dsi_init_link()