1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
20b2e13d9SChunhe Lan /*
30b2e13d9SChunhe Lan * Copyright 2014 Freescale Semiconductor, Inc.
40b2e13d9SChunhe Lan */
50b2e13d9SChunhe Lan
60b2e13d9SChunhe Lan #include <common.h>
70b2e13d9SChunhe Lan #include <command.h>
80b2e13d9SChunhe Lan #include <i2c.h>
90b2e13d9SChunhe Lan #include <netdev.h>
100b2e13d9SChunhe Lan #include <linux/compiler.h>
110b2e13d9SChunhe Lan #include <asm/mmu.h>
120b2e13d9SChunhe Lan #include <asm/processor.h>
130b2e13d9SChunhe Lan #include <asm/cache.h>
140b2e13d9SChunhe Lan #include <asm/immap_85xx.h>
150b2e13d9SChunhe Lan #include <asm/fsl_law.h>
160b2e13d9SChunhe Lan #include <asm/fsl_serdes.h>
170b2e13d9SChunhe Lan #include <asm/fsl_liodn.h>
180b2e13d9SChunhe Lan #include <fm_eth.h>
190b2e13d9SChunhe Lan
200b2e13d9SChunhe Lan #include "t4rdb.h"
21ab06b236SChunhe Lan #include "cpld.h"
222f66a828SYing Zhang #include "../common/vid.h"
230b2e13d9SChunhe Lan
240b2e13d9SChunhe Lan DECLARE_GLOBAL_DATA_PTR;
250b2e13d9SChunhe Lan
checkboard(void)260b2e13d9SChunhe Lan int checkboard(void)
270b2e13d9SChunhe Lan {
280b2e13d9SChunhe Lan struct cpu_type *cpu = gd->arch.cpu;
29ab06b236SChunhe Lan u8 sw;
300b2e13d9SChunhe Lan
310b2e13d9SChunhe Lan printf("Board: %sRDB, ", cpu->name);
32ab06b236SChunhe Lan printf("Board rev: 0x%02x CPLD ver: 0x%02x%02x, ",
33ab06b236SChunhe Lan CPLD_READ(hw_ver), CPLD_READ(sw_maj_ver), CPLD_READ(sw_min_ver));
34ab06b236SChunhe Lan
35ab06b236SChunhe Lan sw = CPLD_READ(vbank);
36ab06b236SChunhe Lan sw = sw & CPLD_BANK_SEL_MASK;
37ab06b236SChunhe Lan
38ab06b236SChunhe Lan if (sw <= 7)
39ab06b236SChunhe Lan printf("vBank: %d\n", sw);
40ab06b236SChunhe Lan else
41ab06b236SChunhe Lan printf("Unsupported Bank=%x\n", sw);
420b2e13d9SChunhe Lan
430b2e13d9SChunhe Lan puts("SERDES Reference Clocks:\n");
440b2e13d9SChunhe Lan printf(" SERDES1=100MHz SERDES2=156.25MHz\n"
450b2e13d9SChunhe Lan " SERDES3=100MHz SERDES4=100MHz\n");
460b2e13d9SChunhe Lan
470b2e13d9SChunhe Lan return 0;
480b2e13d9SChunhe Lan }
490b2e13d9SChunhe Lan
board_early_init_r(void)500b2e13d9SChunhe Lan int board_early_init_r(void)
510b2e13d9SChunhe Lan {
520b2e13d9SChunhe Lan const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
539d045682SYork Sun int flash_esel = find_tlb_idx((void *)flashbase, 1);
540b2e13d9SChunhe Lan
550b2e13d9SChunhe Lan /*
560b2e13d9SChunhe Lan * Remap Boot flash + PROMJET region to caching-inhibited
570b2e13d9SChunhe Lan * so that flash can be erased properly.
580b2e13d9SChunhe Lan */
590b2e13d9SChunhe Lan
600b2e13d9SChunhe Lan /* Flush d-cache and invalidate i-cache of any FLASH data */
610b2e13d9SChunhe Lan flush_dcache();
620b2e13d9SChunhe Lan invalidate_icache();
630b2e13d9SChunhe Lan
649d045682SYork Sun if (flash_esel == -1) {
659d045682SYork Sun /* very unlikely unless something is messed up */
669d045682SYork Sun puts("Error: Could not find TLB for FLASH BASE\n");
679d045682SYork Sun flash_esel = 2; /* give our best effort to continue */
689d045682SYork Sun } else {
690b2e13d9SChunhe Lan /* invalidate existing TLB entry for flash + promjet */
700b2e13d9SChunhe Lan disable_tlb(flash_esel);
719d045682SYork Sun }
720b2e13d9SChunhe Lan
730b2e13d9SChunhe Lan set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
740b2e13d9SChunhe Lan MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
750b2e13d9SChunhe Lan 0, flash_esel, BOOKE_PAGESZ_256M, 1);
760b2e13d9SChunhe Lan
772f66a828SYing Zhang /*
782f66a828SYing Zhang * Adjust core voltage according to voltage ID
792f66a828SYing Zhang * This function changes I2C mux to channel 2.
802f66a828SYing Zhang */
812f66a828SYing Zhang if (adjust_vdd(0))
822f66a828SYing Zhang printf("Warning: Adjusting core voltage failed.\n");
832f66a828SYing Zhang
840b2e13d9SChunhe Lan return 0;
850b2e13d9SChunhe Lan }
860b2e13d9SChunhe Lan
misc_init_r(void)870b2e13d9SChunhe Lan int misc_init_r(void)
880b2e13d9SChunhe Lan {
890b2e13d9SChunhe Lan return 0;
900b2e13d9SChunhe Lan }
910b2e13d9SChunhe Lan
ft_board_setup(void * blob,bd_t * bd)92e895a4b0SSimon Glass int ft_board_setup(void *blob, bd_t *bd)
930b2e13d9SChunhe Lan {
940b2e13d9SChunhe Lan phys_addr_t base;
950b2e13d9SChunhe Lan phys_size_t size;
960b2e13d9SChunhe Lan
970b2e13d9SChunhe Lan ft_cpu_setup(blob, bd);
980b2e13d9SChunhe Lan
99723806ccSSimon Glass base = env_get_bootm_low();
100723806ccSSimon Glass size = env_get_bootm_size();
1010b2e13d9SChunhe Lan
1020b2e13d9SChunhe Lan fdt_fixup_memory(blob, (u64)base, (u64)size);
1030b2e13d9SChunhe Lan
1040b2e13d9SChunhe Lan #ifdef CONFIG_PCI
1050b2e13d9SChunhe Lan pci_of_setup(blob, bd);
1060b2e13d9SChunhe Lan #endif
1070b2e13d9SChunhe Lan
1080b2e13d9SChunhe Lan fdt_fixup_liodn(blob);
109a5c289b9SSriram Dash fsl_fdt_fixup_dr_usb(blob, bd);
1100b2e13d9SChunhe Lan
1110b2e13d9SChunhe Lan #ifdef CONFIG_SYS_DPAA_FMAN
1120b2e13d9SChunhe Lan fdt_fixup_fman_ethernet(blob);
1130b2e13d9SChunhe Lan fdt_fixup_board_enet(blob);
1140b2e13d9SChunhe Lan #endif
115e895a4b0SSimon Glass
116e895a4b0SSimon Glass return 0;
1170b2e13d9SChunhe Lan }
1180b2e13d9SChunhe Lan
1190b2e13d9SChunhe Lan /*
1200b2e13d9SChunhe Lan * This function is called by bdinfo to print detail board information.
1210b2e13d9SChunhe Lan * As an exmaple for future board, we organize the messages into
1220b2e13d9SChunhe Lan * several sections. If applicable, the message is in the format of
1230b2e13d9SChunhe Lan * <name> = <value>
1240b2e13d9SChunhe Lan * It should aligned with normal output of bdinfo command.
1250b2e13d9SChunhe Lan *
1260b2e13d9SChunhe Lan * Voltage: Core, DDR and another configurable voltages
1270b2e13d9SChunhe Lan * Clock : Critical clocks which are not printed already
1280b2e13d9SChunhe Lan * RCW : RCW source if not printed already
1290b2e13d9SChunhe Lan * Misc : Other important information not in above catagories
1300b2e13d9SChunhe Lan */
board_detail(void)1310b2e13d9SChunhe Lan void board_detail(void)
1320b2e13d9SChunhe Lan {
1330b2e13d9SChunhe Lan int rcwsrc;
1340b2e13d9SChunhe Lan
1350b2e13d9SChunhe Lan /* RCW section SW3[4] */
1360b2e13d9SChunhe Lan rcwsrc = 0x0;
1370b2e13d9SChunhe Lan puts("RCW source = ");
1380b2e13d9SChunhe Lan switch (rcwsrc & 0x1) {
1390b2e13d9SChunhe Lan case 0x1:
1400b2e13d9SChunhe Lan puts("SDHC/eMMC\n");
1410b2e13d9SChunhe Lan break;
1420b2e13d9SChunhe Lan default:
1430b2e13d9SChunhe Lan puts("I2C normal addressing\n");
1440b2e13d9SChunhe Lan break;
1450b2e13d9SChunhe Lan }
1460b2e13d9SChunhe Lan }
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