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Searched +full:0 +full:xe6160000 (Results 1 – 25 of 42) sorted by relevance

12

/openbmc/u-boot/board/renesas/ebisu/
H A Debisu.c35 return 0; in board_early_init_f()
41 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; in board_init()
43 return 0; in board_init()
48 if (fdtdec_setup_mem_size_base() != 0) in dram_init()
51 return 0; in dram_init()
58 return 0; in dram_init_banksize()
61 #define RST_BASE 0xE6160000
62 #define RST_CA57RESCNT (RST_BASE + 0x40)
63 #define RST_CA53RESCNT (RST_BASE + 0x44)
64 #define RST_RSTOUTCR (RST_BASE + 0x58)
[all …]
/openbmc/u-boot/board/renesas/eagle/
H A Deagle.c29 #define CPGWPR 0xE6150900
30 #define CPGWPCR 0xE6150904
33 #define PLL0CR 0xE61500D8
34 #define PLL0_STC_MASK 0x7F000000
45 writel(0xA5A5A500, &rwdt->rwtcsra); in s_init()
46 writel(0xA5A5A500, &swdt->swtcsra); in s_init()
56 writel(0xA5A5FFFF, CPGWPR); in board_early_init_f()
57 writel(0x5A5A0000, CPGWPCR); in board_early_init_f()
59 return 0; in board_early_init_f()
65 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; in board_init()
[all …]
/openbmc/u-boot/board/renesas/draak/
H A Ddraak.c44 return 0; in board_early_init_f()
48 #define HSUSB_REG_LPSTS 0xE6590102
50 #define HSUSB_REG_UGCTRL2 0xE6590184
51 #define HSUSB_REG_UGCTRL2_USB0SEL 0x30
52 #define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
57 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; in board_init()
70 return 0; in board_init()
75 if (fdtdec_setup_mem_size_base() != 0) in dram_init()
78 return 0; in dram_init()
85 return 0; in dram_init_banksize()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Drenesas,rst.yaml67 reg = <0xe6160000 0x0200>;
/openbmc/u-boot/board/renesas/salvator-x/
H A Dsalvator-x.c43 return 0; in board_early_init_f()
47 #define HSUSB_REG_LPSTS 0xE6590102
49 #define HSUSB_REG_UGCTRL2 0xE6590184
50 #define HSUSB_REG_UGCTRL2_USB0SEL 0x30
51 #define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
56 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; in board_init()
69 return 0; in board_init()
74 if (fdtdec_setup_mem_size_base() != 0) in dram_init()
77 return 0; in dram_init()
84 return 0; in dram_init_banksize()
[all …]
/openbmc/linux/arch/arm/mach-shmobile/
H A Dpm-rcar-gen2.c21 #define RST 0xe6160000
23 #define CA15BAR 0x0020 /* CA15 Boot Address Register */
24 #define CA7BAR 0x0030 /* CA7 Boot Address Register */
25 #define CA15RESCNT 0x0040 /* CA15 Reset Control Register */
26 #define CA7RESCNT 0x0044 /* CA7 Reset Control Register */
32 #define CA15RESCNT_CODE 0xa5a50000
33 #define CA15RESCNT_CPUS 0xf /* CPU0-3 */
34 #define CA7RESCNT_CODE 0x5a5a0000
35 #define CA7RESCNT_CPUS 0xf /* CPU0-3 */
38 #define ICRAM1 0xe63c0000 /* Inter Connect RAM1 (4 KiB) */
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dr8a77990.dtsi19 #size-cells = <0>;
21 a53_0: cpu@0 {
23 reg = <0>;
39 L2_CA53: cache-controller-0 {
49 #clock-cells = <0>;
51 clock-frequency = <0>;
76 reg = <0 0xe6020000 0 0x0c>;
86 reg = <0 0xe6050000 0 0x50>;
90 gpio-ranges = <&pfc 0 0 18>;
101 reg = <0 0xe6051000 0 0x50>;
[all …]
H A Dr8a7792.dtsi39 #clock-cells = <0>;
41 clock-frequency = <0>;
46 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
69 L2_CA15: cache-controller-0 {
80 #clock-cells = <0>;
82 clock-frequency = <0>;
95 #clock-cells = <0>;
97 clock-frequency = <0>;
[all …]
H A Dr8a77970.dtsi29 #size-cells = <0>;
31 a53_0: cpu@0 {
34 reg = <0>;
61 #clock-cells = <0>;
63 clock-frequency = <0>;
68 #clock-cells = <0>;
70 clock-frequency = <0>;
88 #clock-cells = <0>;
89 clock-frequency = <0>;
95 #clock-cells = <0>;
[all …]
H A Dr8a77995.dtsi21 #clock-cells = <0>;
22 clock-frequency = <0>;
27 #size-cells = <0>;
29 a53_0: cpu@0 {
31 reg = <0x0>;
48 #clock-cells = <0>;
50 clock-frequency = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
79 reg = <0 0xe6020000 0 0x0c>;
[all …]
H A Dr8a7794.dtsi34 * The external audio clocks are configured as 0 Hz fixed frequency
40 #clock-cells = <0>;
41 clock-frequency = <0>;
45 #clock-cells = <0>;
46 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
57 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #size-cells = <0>;
[all …]
H A Dr8a7793.dtsi32 * The external audio clocks are configured as 0 Hz fixed frequency
38 #clock-cells = <0>;
39 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <0>;
55 #clock-cells = <0>;
57 clock-frequency = <0>;
62 #size-cells = <0>;
[all …]
H A Dr8a7791.dtsi40 * The external audio clocks are configured as 0 Hz fixed frequency
46 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
52 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
63 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
H A Dr8a77965.dtsi34 * The external audio clocks are configured as 0 Hz fixed frequency
40 #clock-cells = <0>;
41 clock-frequency = <0>;
46 #clock-cells = <0>;
47 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
59 #clock-cells = <0>;
60 clock-frequency = <0>;
65 #size-cells = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr8a7792.dtsi40 #clock-cells = <0>;
42 clock-frequency = <0>;
47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
71 L2_CA15: cache-controller-0 {
82 #clock-cells = <0>;
84 clock-frequency = <0>;
97 #clock-cells = <0>;
99 clock-frequency = <0>;
[all …]
H A Dr8a77470.dtsi27 #size-cells = <0>;
29 cpu0: cpu@0 {
32 reg = <0>;
51 L2_CA7: cache-controller-0 {
62 #clock-cells = <0>;
64 clock-frequency = <0>;
77 #clock-cells = <0>;
79 clock-frequency = <0>;
93 reg = <0 0xe6020000 0 0x0c>;
104 reg = <0 0xe6050000 0 0x50>;
[all …]
H A Dr8a7794.dtsi34 * The external audio clocks are configured as 0 Hz fixed frequency
40 #clock-cells = <0>;
41 clock-frequency = <0>;
45 #clock-cells = <0>;
46 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
57 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #size-cells = <0>;
[all …]
H A Dr8a7793.dtsi32 * The external audio clocks are configured as 0 Hz fixed frequency
38 #clock-cells = <0>;
39 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <0>;
55 #clock-cells = <0>;
57 clock-frequency = <0>;
62 #size-cells = <0>;
[all …]
H A Dr8a7745.dtsi36 * The external audio clocks are configured as 0 Hz fixed
42 #clock-cells = <0>;
43 clock-frequency = <0>;
47 #clock-cells = <0>;
48 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
59 #clock-cells = <0>;
61 clock-frequency = <0>;
66 #size-cells = <0>;
[all …]
H A Dr8a7742.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
35 #clock-cells = <0>;
36 clock-frequency = <0>;
42 #clock-cells = <0>;
44 clock-frequency = <0>;
49 #size-cells = <0>;
[all …]
H A Dr8a7791.dtsi40 * The external audio clocks are configured as 0 Hz fixed frequency
46 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
52 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
63 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/renesas/
H A Dr8a77970.dtsi22 #clock-cells = <0>;
23 clock-frequency = <0>;
28 #size-cells = <0>;
30 a53_0: cpu@0 {
33 reg = <0>;
60 #clock-cells = <0>;
62 clock-frequency = <0>;
67 #clock-cells = <0>;
69 clock-frequency = <0>;
87 #clock-cells = <0>;
[all …]
H A Dr8a779f0.dtsi17 cluster01_opp: opp-table-0 {
73 #size-cells = <0>;
113 a55_0: cpu@0 {
115 reg = <0>;
127 reg = <0x100>;
139 reg = <0x10000>;
151 reg = <0x10100>;
163 reg = <0x20000>;
175 reg = <0x20100>;
187 reg = <0x30000>;
[all …]
H A Dr8a77980.dtsi22 #clock-cells = <0>;
23 clock-frequency = <0>;
28 #size-cells = <0>;
30 a53_0: cpu@0 {
33 reg = <0>;
80 #clock-cells = <0>;
82 clock-frequency = <0>;
87 #clock-cells = <0>;
89 clock-frequency = <0>;
95 #clock-cells = <0>;
[all …]
H A Dr8a77995.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
38 #clock-cells = <0>;
39 clock-frequency = <0>;
44 #size-cells = <0>;
46 a53_0: cpu@0 {
48 reg = <0x0>;
[all …]

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