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Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48 |
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| #
05c618f3 |
| 23-Aug-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: use capital "OR" for multiple licenses in SPDX
Documentation/process/license-rules.rst and checkpatch expect the SPDX
identifier syntax for multiple licenses to use capital "OR". Correc
arm64: dts: use capital "OR" for multiple licenses in SPDX
Documentation/process/license-rules.rst and checkpatch expect the SPDX
identifier syntax for multiple licenses to use capital "OR". Correct it
to keep consistent format and avoid copy-paste issues.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Florian Fainelli <florian.fainelli@broadcom.com> # Broadcom
Link: https://lore.kernel.org/r/20230823085146.113562-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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|
Revision tags: v6.1.46, v6.1.45, v6.1.44, v6.1.43 |
|
| #
b4dee778 |
| 27-Jul-2023 |
Geert Uytterhoeven <geert+renesas@glider.be> |
arm64: dts: renesas: r8a779f0: Add INTC-EX node
Add the device node for the Interrupt Controller for External Devices
(INTC-EX) on the Renesas R-Car S4-8 (R8A779F0) SoC, which serves
external IRQ pi
arm64: dts: renesas: r8a779f0: Add INTC-EX node
Add the device node for the Interrupt Controller for External Devices
(INTC-EX) on the Renesas R-Car S4-8 (R8A779F0) SoC, which serves
external IRQ pins IRQ[0-5].
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/8f5612c0353b8c90f98366978563340d93c7ae58.1690447013.git.geert+renesas@glider.be
show more ...
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|
Revision tags: v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8 |
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| #
a1c11b34 |
| 22-Jan-2023 |
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> |
arm64: dts: renesas: r8a779f0: Revise renesas,ipmmu-main
Since IMSSTR register was undocumented on the latest datasheet and
dt-bindings of renesas,ipmmu-vmsa was updated about
the renesas,ipmmu-main
arm64: dts: renesas: r8a779f0: Revise renesas,ipmmu-main
Since IMSSTR register was undocumented on the latest datasheet and
dt-bindings of renesas,ipmmu-vmsa was updated about
the renesas,ipmmu-main property, revise the property on each cache
IPMMU node.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20230123013448.1250991-2-yoshihiro.shimoda.uh@renesas.com
[geert: Drop indices from renesas,ipmmu-main properties]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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| #
109e28af |
| 09-Feb-2023 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
arm64: dts: renesas: r8a779f0: Use proper labels for thermal zones
The documentation provides information about the placement of the zones,
so that can be used for more descriptive labels.
Signed-o
arm64: dts: renesas: r8a779f0: Use proper labels for thermal zones
The documentation provides information about the placement of the zones,
so that can be used for more descriptive labels.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230209200735.3882-1-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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| #
8b6a006c |
| 05-Feb-2023 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
arm64: dts: renesas: Drop specifying the GIC_CPU_MASK_SIMPLE() for GICv3 systems
The GICv3 interrupts binding does not have a cpumask. The CPU mask only
applies to pre-GICv3. So just drop using them
arm64: dts: renesas: Drop specifying the GIC_CPU_MASK_SIMPLE() for GICv3 systems
The GICv3 interrupts binding does not have a cpumask. The CPU mask only
applies to pre-GICv3. So just drop using them from GICv3 systems.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230206002136.29401-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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| #
46fe3950 |
| 22-Jan-2023 |
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> |
arm64: dts: renesas: r8a779f0: Add iommus to MMC node
Add iommus property to the MMC node for r8a779f0.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytter
arm64: dts: renesas: r8a779f0: Add iommus to MMC node
Add iommus property to the MMC node for r8a779f0.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230123013448.1250991-3-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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|
Revision tags: v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11 |
|
| #
ef10e647 |
| 30-Nov-2022 |
Geert Uytterhoeven <geert+renesas@glider.be> |
arm64: dts: renesas: r8a779f0: Add CA55 operating points
Add operating points for running the Cortex-A55 CPU cores on R-Car S4-8
at various speeds, up to the maximum supported frequency (1200 MHz).
arm64: dts: renesas: r8a779f0: Add CA55 operating points
Add operating points for running the Cortex-A55 CPU cores on R-Car S4-8
at various speeds, up to the maximum supported frequency (1200 MHz).
R-Car S4-8 has 8 Cortex-A55 cores, grouped in 4 clusters.
CA55 Sub-System 0 (first 2 clusters / CPU cores 0-3) is clocked by Z0φ.
CA55 Sub-System 1 (last 2 clusters / CPU cores 4-7) is clocked by Z1φ.
As the two sets of clusters are driven by separate clocks, this requires
specifying two separate tables (using the same operating performance
point values), with "opp-shared" to indicate that the CPU cores in each
set share state.
Based on a patch in the BSP by Tho Vu.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Link: https://lore.kernel.org/r/ae78351d702a53702a1d5fa26675fe982b99cdf5.1669817508.git.geert+renesas@glider.be
show more ...
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|
Revision tags: v6.0.10, v5.15.80 |
|
| #
387e16cb |
| 18-Nov-2022 |
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> |
arm64: dts: renesas: r8a779f0: Add Ethernet Switch and SERDES nodes
Add Ethernet Switch and SERDES nodes into R-Car S4-8 (r8a779f0).
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.c
arm64: dts: renesas: r8a779f0: Add Ethernet Switch and SERDES nodes
Add Ethernet Switch and SERDES nodes into R-Car S4-8 (r8a779f0).
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20221118120953.1186392-2-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Revision tags: v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77 |
|
| #
64416ef0 |
| 03-Nov-2022 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
arm64: dts: renesas: r8a779f0: Fix SCIF "brg_int" clock
As serial communication requires a clean clock signal, the Serial
Communication Interfaces with FIFO (SCIF) are clocked by a clock that is
not
arm64: dts: renesas: r8a779f0: Fix SCIF "brg_int" clock
As serial communication requires a clean clock signal, the Serial
Communication Interfaces with FIFO (SCIF) are clocked by a clock that is
not affected by Spread Spectrum or Fractional Multiplication.
Hence change the clock input for the SCIF Baud Rate Generator internal
clock from the S0D3_PER clock to the SASYNCPERD1 clock (which has the
same clock rate), cfr. R-Car S4-8 Hardware User's Manual rev. 0.81.
Fixes: c62331e8222f ("arm64: dts: renesas: Add Renesas R8A779F0 SoC support")
Fixes: 40753144256b ("arm64: dts: renesas: r8a779f0: Add SCIF nodes")
Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20221103143440.46449-5-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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| #
a5101ef1 |
| 03-Nov-2022 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
arm64: dts: renesas: r8a779f0: Fix HSCIF "brg_int" clock
As serial communication requires a clean clock signal, the High Speed
Serial Communication Interfaces with FIFO (HSCIF) are clocked by a cloc
arm64: dts: renesas: r8a779f0: Fix HSCIF "brg_int" clock
As serial communication requires a clean clock signal, the High Speed
Serial Communication Interfaces with FIFO (HSCIF) are clocked by a clock
that is not affected by Spread Spectrum or Fractional Multiplication.
Hence change the clock input for the HSCIF Baud Rate Generator internal
clock from the S0D3_PER clock to the SASYNCPERD1 clock (which has the
same clock rate), cfr. R-Car S4-8 Hardware User's Manual rev. 0.81.
Fixes: 01a787f78bfd ("arm64: dts: renesas: r8a779f0: Add HSCIF nodes")
Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20221103143440.46449-4-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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|
Revision tags: v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64 |
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| #
1cc6987e |
| 29-Aug-2022 |
Duc Nguyen <duc.nguyen.ub@renesas.com> |
arm64: dts: renesas: r8a779f0: Add MSIOF nodes
Add MSIOF nodes for R-Car S4-8.
Signed-off-by: Duc Nguyen <duc.nguyen.ub@renesas.com>
[thanh: added DMA]
Signed-off-by: Thanh Quan <thanh.quan.xn@rene
arm64: dts: renesas: r8a779f0: Add MSIOF nodes
Add MSIOF nodes for R-Car S4-8.
Signed-off-by: Duc Nguyen <duc.nguyen.ub@renesas.com>
[thanh: added DMA]
Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com>
[wsa: removed mso clock from clocks-property]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220829124130.2412-1-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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|
Revision tags: v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58 |
|
| #
7adc69f8 |
| 26-Jul-2022 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
arm64: dts: renesas: r8a779f0: Add TMU nodes
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220726210110.1444-3-wsa+renesas@sang-engineering.com
Sig
arm64: dts: renesas: r8a779f0: Add TMU nodes
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220726210110.1444-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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|
Revision tags: v5.15.57, v5.15.56, v5.15.55 |
|
| #
d227fcc3 |
| 13-Jul-2022 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
arm64: dts: renesas: r8a779f0: Add CMT support
This patch adds CMT{0|1|2|3} device nodes for R-Car S4-8 (r8a779f0) SoC.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://
arm64: dts: renesas: r8a779f0: Add CMT support
This patch adds CMT{0|1|2|3} device nodes for R-Car S4-8 (r8a779f0) SoC.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220713101447.3804-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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|
Revision tags: v5.15.54 |
|
| #
6a24768c |
| 11-Jul-2022 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
arm64: dts: renesas: r8a779f0: Add SDHI0 support
Extracted from a larger BSP patch made by Linh Phung.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Yoshihiro Shimoda
arm64: dts: renesas: r8a779f0: Add SDHI0 support
Extracted from a larger BSP patch made by Linh Phung.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20220711134656.277730-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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|
Revision tags: v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47 |
|
| #
40753144 |
| 14-Jun-2022 |
Linh Phung <linh.phung.jy@renesas.com> |
arm64: dts: renesas: r8a779f0: Add SCIF nodes
Extracted from a bigger patch in the BSP, rebased, reg length corrected,
and DMA properties added.
Signed-off-by: Linh Phung <linh.phung.jy@renesas.com
arm64: dts: renesas: r8a779f0: Add SCIF nodes
Extracted from a bigger patch in the BSP, rebased, reg length corrected,
and DMA properties added.
Signed-off-by: Linh Phung <linh.phung.jy@renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220614095242.8264-1-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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| #
01a787f7 |
| 14-Jun-2022 |
Linh Phung <linh.phung.jy@renesas.com> |
arm64: dts: renesas: r8a779f0: Add HSCIF nodes
Extracted from a bigger patch in the BSP, rebased and DMA
properties added.
Signed-off-by: Linh Phung <linh.phung.jy@renesas.com>
Signed-off-by: Wolfr
arm64: dts: renesas: r8a779f0: Add HSCIF nodes
Extracted from a bigger patch in the BSP, rebased and DMA
properties added.
Signed-off-by: Linh Phung <linh.phung.jy@renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220614095109.8175-1-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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| #
c62872a6 |
| 13-Jun-2022 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
arm64: dts: renesas: r8a779f0: Add DMA properties to SCIF3
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220613134914.18655-1-wsa+renesas@sang-engi
arm64: dts: renesas: r8a779f0: Add DMA properties to SCIF3
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220613134914.18655-1-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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|
|
Revision tags: v5.15.46 |
|
| #
e5fba0bc |
| 08-Jun-2022 |
Geert Uytterhoeven <geert+renesas@glider.be> |
arm64: dts: renesas: r8a779f0: Add CPU core clocks
Describe the clocks for the eight Cortex-A55 CPU cores.
CA55 Sub-System 0 (first 2 clusters / CPU cores 0-3) is clocked by Z0φ.
CA55 Sub-System 1 (
arm64: dts: renesas: r8a779f0: Add CPU core clocks
Describe the clocks for the eight Cortex-A55 CPU cores.
CA55 Sub-System 0 (first 2 clusters / CPU cores 0-3) is clocked by Z0φ.
CA55 Sub-System 1 (last 2 clusters / CPU cores 4-7) is clocked by Z1φ.
For now no operating points are defined.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/c502087f9affa86dd665def0d990d277a51cc75c.1654701480.git.geert+renesas@glider.be
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| #
9bc7cd07 |
| 08-Jun-2022 |
Tho Vu <tho.vu.wh@renesas.com> |
arm64: dts: renesas: r8a779f0: Add CPUIdle support
Support CPUIdle for ARM Cortex-A55 on R-Car S4-8.
Signed-off-by: Tho Vu <tho.vu.wh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@g
arm64: dts: renesas: r8a779f0: Add CPUIdle support
Support CPUIdle for ARM Cortex-A55 on R-Car S4-8.
Signed-off-by: Tho Vu <tho.vu.wh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/5310792ce4c06515a5373ff44ceb9b925f007489.1654701480.git.geert+renesas@glider.be
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|
| #
2dcb78d2 |
| 08-Jun-2022 |
Geert Uytterhoeven <geert+renesas@glider.be> |
arm64: dts: renesas: r8a779f0: Add secondary CA55 CPU cores
Complete the description of the Cortex-A55 CPU cores and L3 cache
controllers on the Renesas R-Car S4-8 (R8A779F0) SoC, including CPU
topo
arm64: dts: renesas: r8a779f0: Add secondary CA55 CPU cores
Complete the description of the Cortex-A55 CPU cores and L3 cache
controllers on the Renesas R-Car S4-8 (R8A779F0) SoC, including CPU
topology and PSCI support for enabling CPU cores.
R-Car S4-8 has 8 Cortex-A55 cores, grouped in 4 clusters.
Based on patches in the BSP by Takeshi Kihara.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/d6af5975090d5830cb053b52400439bd1cbe8fc7.1654701480.git.geert+renesas@glider.be
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| #
ffeca49a |
| 08-Jun-2022 |
Geert Uytterhoeven <geert+renesas@glider.be> |
arm64: dts: renesas: r8a779f0: Add L3 cache controller
Describe the cache configuration for the first Cortex-A55 CPU core on
the Renesas R-Car S4-8 (R8A779F0) SoC.
Extracted from a larger patch in
arm64: dts: renesas: r8a779f0: Add L3 cache controller
Describe the cache configuration for the first Cortex-A55 CPU core on
the Renesas R-Car S4-8 (R8A779F0) SoC.
Extracted from a larger patch in the BSP by LUU HOAI.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/a63715ce1d2d2fcc7ab987f7a1b40847965e8d6a.1654701480.git.geert+renesas@glider.be
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Revision tags: v5.15.45 |
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| #
5235d551 |
| 03-Jun-2022 |
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> |
arm64: dts: renesas: r8a779f0: Add UFS node
Add UFS node for R-Car S4-8 (r8a779f0).
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesa
arm64: dts: renesas: r8a779f0: Add UFS node
Add UFS node for R-Car S4-8 (r8a779f0).
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20220603110524.1997825-7-yoshihiro.shimoda.uh@renesas.com
[geert: Move ufs30-clk to preserve sort order]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Revision tags: v5.15.44 |
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| #
3a9747f0 |
| 29-May-2022 |
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> |
arm64: dts: renesas: r8a779f0: Add iommus to DMAC nodes
Add iommus properties to the DMAC nodes for r8a779f0.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.
arm64: dts: renesas: r8a779f0: Add iommus to DMAC nodes
Add iommus properties to the DMAC nodes for r8a779f0.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20220530024626.1870277-3-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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| #
fd869e63 |
| 29-May-2022 |
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> |
arm64: dts: renesas: r8a779f0: Add IPMMU nodes
Add IPMMU nodes for r8a779f0.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20220530024626.18702
arm64: dts: renesas: r8a779f0: Add IPMMU nodes
Add IPMMU nodes for r8a779f0.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20220530024626.1870277-2-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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| #
5a3ad6f4 |
| 25-May-2022 |
Linh Phung <linh.phung.jy@renesas.com> |
arm64: dts: renesas: r8a779f0: Add thermal support
Add support for 3 TSC nodes of thermal. The 4th node is for the control
domain and not for Linux.
Signed-off-by: Linh Phung <linh.phung.jy@renesas
arm64: dts: renesas: r8a779f0: Add thermal support
Add support for 3 TSC nodes of thermal. The 4th node is for the control
domain and not for Linux.
Signed-off-by: Linh Phung <linh.phung.jy@renesas.com>
[wsa: rebased, fixed resource size, removed unused 4th node breaking probe]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220525151355.24175-1-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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