Lines Matching +full:0 +full:xe6160000
34 * The external audio clocks are configured as 0 Hz fixed frequency
40 #clock-cells = <0>;
41 clock-frequency = <0>;
46 #clock-cells = <0>;
47 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
59 #clock-cells = <0>;
60 clock-frequency = <0>;
65 #size-cells = <0>;
67 a57_0: cpu@0 {
69 reg = <0x0>;
78 reg = <0x1>;
85 L2_CA57: cache-controller-0 {
95 #clock-cells = <0>;
97 clock-frequency = <0>;
102 #clock-cells = <0>;
104 clock-frequency = <0>;
110 #clock-cells = <0>;
111 clock-frequency = <0>;
130 #clock-cells = <0>;
131 clock-frequency = <0>;
144 reg = <0 0xe6020000 0 0x0c>;
154 reg = <0 0xe6050000 0 0x50>;
158 gpio-ranges = <&pfc 0 0 16>;
169 reg = <0 0xe6051000 0 0x50>;
173 gpio-ranges = <&pfc 0 32 29>;
184 reg = <0 0xe6052000 0 0x50>;
188 gpio-ranges = <&pfc 0 64 15>;
199 reg = <0 0xe6053000 0 0x50>;
203 gpio-ranges = <&pfc 0 96 16>;
214 reg = <0 0xe6054000 0 0x50>;
218 gpio-ranges = <&pfc 0 128 18>;
229 reg = <0 0xe6055000 0 0x50>;
233 gpio-ranges = <&pfc 0 160 26>;
244 reg = <0 0xe6055400 0 0x50>;
248 gpio-ranges = <&pfc 0 192 32>;
259 reg = <0 0xe6055800 0 0x50>;
263 gpio-ranges = <&pfc 0 224 4>;
273 reg = <0 0xe6060000 0 0x50c>;
278 reg = <0 0xe6150000 0 0x1000>;
282 #power-domain-cells = <0>;
288 reg = <0 0xe6160000 0 0x0200>;
293 reg = <0 0xe6180000 0 0x0400>;
299 reg = <0 0xe6198000 0 0x100>,
300 <0 0xe61a0000 0 0x100>,
301 <0 0xe61a8000 0 0x100>;
316 reg = <0 0xe61c0000 0 0x200>;
317 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
330 #size-cells = <0>;
333 reg = <0 0xe6500000 0 0x40>;
338 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
339 <&dmac2 0x91>, <&dmac2 0x90>;
347 #size-cells = <0>;
350 reg = <0 0xe6508000 0 0x40>;
355 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
356 <&dmac2 0x93>, <&dmac2 0x92>;
364 #size-cells = <0>;
367 reg = <0 0xe6510000 0 0x40>;
372 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
373 <&dmac2 0x95>, <&dmac2 0x94>;
381 #size-cells = <0>;
384 reg = <0 0xe66d0000 0 0x40>;
389 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
397 #size-cells = <0>;
400 reg = <0 0xe66d8000 0 0x40>;
405 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
413 #size-cells = <0>;
416 reg = <0 0xe66e0000 0 0x40>;
421 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
429 #size-cells = <0>;
432 reg = <0 0xe66e8000 0 0x40>;
437 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
445 #size-cells = <0>;
449 reg = <0 0xe60b0000 0 0x425>;
454 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
463 reg = <0 0xe6540000 0 0x60>;
469 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
470 <&dmac2 0x31>, <&dmac2 0x30>;
481 reg = <0 0xe6550000 0 0x60>;
487 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
488 <&dmac2 0x33>, <&dmac2 0x32>;
499 reg = <0 0xe6560000 0 0x60>;
505 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
506 <&dmac2 0x35>, <&dmac2 0x34>;
517 reg = <0 0xe66a0000 0 0x60>;
523 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
534 reg = <0 0xe66b0000 0 0x60>;
540 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
550 reg = <0 0xe6590000 0 0x100>;
553 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
554 <&usb_dmac1 0>, <&usb_dmac1 1>;
567 reg = <0 0xe65a0000 0 0x100>;
581 reg = <0 0xe65b0000 0 0x100>;
595 reg = <0 0xe65ee000 0 0x90>;
601 #phy-cells = <0>;
608 reg = <0 0xe6700000 0 0x10000>;
642 reg = <0 0xe7300000 0 0x10000>;
676 reg = <0 0xe7310000 0 0x10000>;
709 reg = <0 0xe6740000 0 0x1000>;
710 renesas,ipmmu-main = <&ipmmu_mm 0>;
717 reg = <0 0xe7740000 0 0x1000>;
725 reg = <0 0xe6570000 0 0x1000>;
733 reg = <0 0xff8b0000 0 0x1000>;
741 reg = <0 0xe67b0000 0 0x1000>;
750 reg = <0 0xec670000 0 0x1000>;
758 reg = <0 0xfd800000 0 0x1000>;
766 reg = <0 0xffc80000 0 0x1000>;
774 reg = <0 0xfe6b0000 0 0x1000>;
782 reg = <0 0xfebd0000 0 0x1000>;
790 reg = <0 0xfe990000 0 0x1000>;
799 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
837 #size-cells = <0>;
843 reg = <0 0xe6e30000 0 8>;
853 reg = <0 0xe6e31000 0 8>;
863 reg = <0 0xe6e32000 0 8>;
873 reg = <0 0xe6e33000 0 8>;
883 reg = <0 0xe6e34000 0 8>;
893 reg = <0 0xe6e35000 0 8>;
903 reg = <0 0xe6e36000 0 8>;
914 reg = <0 0xe6e60000 0 64>;
920 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
921 <&dmac2 0x51>, <&dmac2 0x50>;
931 reg = <0 0xe6e68000 0 64>;
937 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
938 <&dmac2 0x53>, <&dmac2 0x52>;
948 reg = <0 0xe6e88000 0 64>;
962 reg = <0 0xe6c50000 0 64>;
968 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
978 reg = <0 0xe6c40000 0 64>;
984 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
994 reg = <0 0xe6f30000 0 64>;
1000 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1001 <&dmac2 0x5b>, <&dmac2 0x5a>;
1011 reg = <0 0xe6e90000 0 0x0064>;
1014 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1015 <&dmac2 0x41>, <&dmac2 0x40>;
1020 #size-cells = <0>;
1027 reg = <0 0xe6ea0000 0 0x0064>;
1030 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1031 <&dmac2 0x43>, <&dmac2 0x42>;
1036 #size-cells = <0>;
1043 reg = <0 0xe6c00000 0 0x0064>;
1046 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1051 #size-cells = <0>;
1058 reg = <0 0xe6c10000 0 0x0064>;
1061 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1066 #size-cells = <0>;
1072 reg = <0 0xe6ef0000 0 0x1000>;
1077 renesas,id = <0>;
1082 #size-cells = <0>;
1086 #size-cells = <0>;
1090 vin0csi20: endpoint@0 {
1091 reg = <0>;
1104 reg = <0 0xe6ef1000 0 0x1000>;
1114 #size-cells = <0>;
1118 #size-cells = <0>;
1122 vin1csi20: endpoint@0 {
1123 reg = <0>;
1136 reg = <0 0xe6ef2000 0 0x1000>;
1146 #size-cells = <0>;
1150 #size-cells = <0>;
1154 vin2csi20: endpoint@0 {
1155 reg = <0>;
1168 reg = <0 0xe6ef3000 0 0x1000>;
1178 #size-cells = <0>;
1182 #size-cells = <0>;
1186 vin3csi20: endpoint@0 {
1187 reg = <0>;
1200 reg = <0 0xe6ef4000 0 0x1000>;
1210 #size-cells = <0>;
1214 #size-cells = <0>;
1218 vin4csi20: endpoint@0 {
1219 reg = <0>;
1232 reg = <0 0xe6ef5000 0 0x1000>;
1242 #size-cells = <0>;
1246 #size-cells = <0>;
1250 vin5csi20: endpoint@0 {
1251 reg = <0>;
1264 reg = <0 0xe6ef6000 0 0x1000>;
1274 #size-cells = <0>;
1278 #size-cells = <0>;
1282 vin6csi20: endpoint@0 {
1283 reg = <0>;
1296 reg = <0 0xe6ef7000 0 0x1000>;
1306 #size-cells = <0>;
1310 #size-cells = <0>;
1314 vin7csi20: endpoint@0 {
1315 reg = <0>;
1327 reg = <0 0xec500000 0 0x1000>, /* SCU */
1328 <0 0xec5a0000 0 0x100>, /* ADG */
1329 <0 0xec540000 0 0x1000>, /* SSIU */
1330 <0 0xec541000 0 0x280>, /* SSI */
1331 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1335 dvc0: dvc-0 {
1342 src0: src-0 {
1349 ssi0: ssi-0 {
1357 #size-cells = <0>;
1358 port@0 {
1359 reg = <0>;
1370 reg = <0 0xee000000 0 0xc00>;
1381 reg = <0 0xee020000 0 0x400>;
1391 reg = <0 0xee080000 0 0x100>;
1403 reg = <0 0xee0a0000 0 0x100>;
1415 reg = <0 0xee080100 0 0x100>;
1428 reg = <0 0xee0a0100 0 0x100>;
1442 reg = <0 0xee080200 0 0x700>;
1447 #phy-cells = <0>;
1454 reg = <0 0xee0a0200 0 0x700>;
1458 #phy-cells = <0>;
1465 reg = <0 0xee100000 0 0x2000>;
1477 reg = <0 0xee120000 0 0x2000>;
1489 reg = <0 0xee140000 0 0x2000>;
1501 reg = <0 0xee160000 0 0x2000>;
1513 #address-cells = <0>;
1515 reg = <0x0 0xf1010000 0 0x1000>,
1516 <0x0 0xf1020000 0 0x20000>,
1517 <0x0 0xf1040000 0 0x20000>,
1518 <0x0 0xf1060000 0 0x20000>;
1530 reg = <0 0xfe000000 0 0x80000>;
1533 bus-range = <0x00 0xff>;
1535 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1536 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1537 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1538 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1540 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
1545 interrupt-map-mask = <0 0 0 0>;
1546 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1557 reg = <0 0xee800000 0 0x80000>;
1560 bus-range = <0x00 0xff>;
1562 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000
1563 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000
1564 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000
1565 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
1567 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
1572 interrupt-map-mask = <0 0 0 0>;
1573 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1583 reg = <0 0xfe950000 0 0x200>;
1591 reg = <0 0xfe960000 0 0x8000>;
1602 reg = <0 0xfe96f000 0 0x200>;
1610 reg = <0 0xfe9a0000 0 0x8000>;
1621 reg = <0 0xfe9af000 0 0x200>;
1629 reg = <0 0xfea20000 0 0x5000>;
1640 reg = <0 0xfea27000 0 0x200>;
1648 reg = <0 0xfea28000 0 0x5000>;
1659 reg = <0 0xfea2f000 0 0x200>;
1667 reg = <0 0xfea80000 0 0x10000>;
1676 #size-cells = <0>;
1680 #size-cells = <0>;
1684 csi20vin0: endpoint@0 {
1685 reg = <0>;
1722 reg = <0 0xfeaa0000 0 0x10000>;
1731 #size-cells = <0>;
1735 #size-cells = <0>;
1739 csi40vin0: endpoint@0 {
1740 reg = <0>;
1778 reg = <0 0xfead0000 0 0x10000>;
1789 #size-cells = <0>;
1790 port@0 {
1791 reg = <0>;
1804 reg = <0 0xfeb00000 0 0x80000>;
1812 clock-names = "du.0", "du.1", "du.3";
1815 vsps = <&vspd0 0 &vspd1 0 &vspd0 1>;
1819 #size-cells = <0>;
1821 port@0 {
1822 reg = <0>;
1842 reg = <0 0xfff00044 0 4>;
1858 thermal-sensors = <&tsc 0>;
1901 #clock-cells = <0>;
1902 clock-frequency = <0>;
1907 #clock-cells = <0>;
1908 clock-frequency = <0>;