Lines Matching +full:0 +full:xe6160000
29 #define CPGWPR 0xE6150900
30 #define CPGWPCR 0xE6150904
33 #define PLL0CR 0xE61500D8
34 #define PLL0_STC_MASK 0x7F000000
45 writel(0xA5A5A500, &rwdt->rwtcsra); in s_init()
46 writel(0xA5A5A500, &swdt->swtcsra); in s_init()
56 writel(0xA5A5FFFF, CPGWPR); in board_early_init_f()
57 writel(0x5A5A0000, CPGWPCR); in board_early_init_f()
59 return 0; in board_early_init_f()
65 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; in board_init()
67 return 0; in board_init()
72 if (fdtdec_setup_mem_size_base() != 0) in dram_init()
75 return 0; in dram_init()
82 return 0; in dram_init_banksize()
85 #define RST_BASE 0xE6160000
86 #define RST_CA57RESCNT (RST_BASE + 0x40)
87 #define RST_CA53RESCNT (RST_BASE + 0x44)
88 #define RST_RSTOUTCR (RST_BASE + 0x58)
89 #define RST_CA57_CODE 0xA5A5000F
90 #define RST_CA53_CODE 0x5A5A000F
96 asm volatile("mrs %0, midr_el1" : "=r" (midr)); in reset_cpu()
97 cputype = (midr >> 4) & 0xfff; in reset_cpu()
99 if (cputype == 0xd03) in reset_cpu()
101 else if (cputype == 0xd07) in reset_cpu()