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/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8536ds.dts17 #size-cells = <0>;
19 PowerPC,8536@0 {
21 reg = <0>;
28 reg = <0 0 0 0>; // Filled by U-Boot
32 reg = <0 0xffe05000 0 0x1000>;
34 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
35 0x2 0x0 0x0 0xffa00000 0x00040000
36 0x3 0x0 0x0 0xffdf0000 0x00008000>;
40 ranges = <0x0 0 0xffe00000 0x100000>;
44 reg = <0 0xffe08000 0 0x1000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/realtek/
H A Drtd139x.dtsi8 /memreserve/ 0x0000000000000000 0x000000000002f000;
9 /memreserve/ 0x000000000002f000 0x00000000000d1000;
25 reg = <0x2f000 0x1000>;
29 reg = <0x1ffe000 0x4000>;
33 reg = <0x10100000 0xf00000>;
46 #clock-cells = <0>;
54 ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */
55 <0x98000000 0x98000000 0x68000000>;
59 reg = <0x98000000 0x200000>;
62 ranges = <0x0 0x98000000 0x200000>;
[all …]
H A Drtd16xx.dtsi23 reg = <0x2f000 0x1000>;
27 reg = <0x1ffe000 0x4000>;
31 reg = <0x10100000 0xf00000>;
38 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0x0>;
51 reg = <0x100>;
59 reg = <0x200>;
67 reg = <0x300>;
75 reg = <0x400>;
[all …]
H A Drtd129x.dtsi8 /memreserve/ 0x0000000000000000 0x000000000001f000;
9 /memreserve/ 0x000000000001f000 0x00000000000e1000;
10 /memreserve/ 0x0000000001b00000 0x00000000004be000;
26 reg = <0x1f000 0x1000>;
30 reg = <0x1ffe000 0x4000>;
34 reg = <0x10100000 0xf00000>;
47 #clock-cells = <0>;
55 ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */
57 <0x80000000 0x80000000 0x80000000>;
61 reg = <0x98000000 0x200000>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dopenrisc,ompic.txt10 - #interrupt-cells : This should be set to 0 as this will not be an irq
18 reg = <0x98000000 16>;
20 #interrupt-cells = <0>;
/openbmc/linux/arch/openrisc/boot/dts/
H A Dsimple_smp.dts17 memory@0 {
19 reg = <0x00000000 0x02000000>;
24 #size-cells = <0>;
25 cpu@0 {
27 reg = <0>;
39 reg = <0x98000000 16>;
41 #interrupt-cells = <0>;
58 reg = <0x90000000 0x100>;
65 reg = <0x92000000 0x800>;
/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip05-d02.dts17 memory@0 {
19 reg = <0x0 0x00000000 0x0 0x80000000>;
37 debounce-interval = <0>;
54 ranges = <0 0 0x0 0x90000000 0x08000000>,
55 <1 0 0x0 0x98000000 0x08000000>;
57 nor-flash@0,0 {
61 reg = <0 0x0 0x08000000>;
64 partition@0 {
66 reg = <0x0 0x300000>;
70 reg = <0x300000 0xa00000>;
[all …]
/openbmc/u-boot/include/configs/
H A DMPC8536DS.h17 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
22 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
26 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
62 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */
63 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */
68 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
70 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
77 #define CONFIG_SYS_CCSRBAR 0xffe00000
90 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
92 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
[all …]
/openbmc/u-boot/arch/arm/mach-orion5x/include/mach/
H A Dcpu.h22 ((_x ? ORION5X_EGIGA0_BASE : ORION5X_EGIGA1_BASE) + 0x44c)
37 ORION5X_TARGET_DRAM = 0,
45 ORION5X_ATTR_DRAM_CS0 = 0x0e,
46 ORION5X_ATTR_DRAM_CS1 = 0x0d,
47 ORION5X_ATTR_DRAM_CS2 = 0x0b,
48 ORION5X_ATTR_DRAM_CS3 = 0x07,
49 ORION5X_ATTR_PCI_MEM = 0x59,
50 ORION5X_ATTR_PCI_IO = 0x51,
51 ORION5X_ATTR_PCIE_MEM = 0x59,
52 ORION5X_ATTR_PCIE_IO = 0x51,
[all …]
/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-opp-lanyang.dts18 reg = <0x80000000 0x40000000>;
28 reg = <0x98000000 0x04000000>; /* 64M */
68 #size-cells = <0>;
70 clock-gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_HIGH>;
73 enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
79 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
94 pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default
97 fan@0 {
98 reg = <0x00>;
99 aspeed,fan-tach-ch = /bits/ 8 <0x00>;
[all …]
H A Daspeed-bmc-opp-nicole.dts17 reg = <0x80000000 0x20000000>;
27 reg = <0x9f000000 0x01000000>; /* 16M */
32 reg = <0x98000000 0x04000000>; /* 64M */
36 reg = <0x9ef00000 0x00100000>;
41 size = <0x01000000>;
42 alignment = <0x01000000>;
48 size = <0x02000000>; /* 32M */
49 alignment = <0x01000000>;
82 #size-cells = <0>;
89 clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
[all …]
H A Daspeed-bmc-opp-romulus.dts16 reg = <0x80000000 0x20000000>;
26 reg = <0x9f000000 0x01000000>; /* 16M */
31 reg = <0x98000000 0x04000000>; /* 64M */
35 reg = <0x9ef00000 0x00100000>;
40 size = <0x01000000>;
41 alignment = <0x01000000>;
47 size = <0x02000000>; /* 32M */
48 alignment = <0x01000000>;
73 #size-cells = <0>;
80 clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>;
[all …]
H A Daspeed-bmc-lenovo-hr630.dts35 reg = <0x80000000 0x20000000>;
45 reg = <0x98000000 0x00100000>; /* 1M */
49 size = <0x01000000>;
50 alignment = <0x01000000>;
64 gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>;
70 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
80 flash@0 {
98 pinctrl-0 = <&pinctrl_txd1_default
106 pinctrl-0 = <&pinctrl_txd2_default
119 pinctrl-0 = <&pinctrl_txd3_default
[all …]
/openbmc/linux/tools/testing/selftests/powerpc/include/
H A Dinstructions.h10 (0x7c00060c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10))
16 asm volatile(str(COPY(0, %0, 0))";" in copy()
25 asm volatile(str(COPY(0, %0, 1))";" in copy_first()
34 (0x7c00070c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10) | (RC) << (31-31))
42 asm volatile(str(PASTE(0, %1, 0, 0))";" in paste()
43 "mfcr %0;" in paste()
55 asm volatile(str(PASTE(0, %1, 1, 1))";" in paste_last()
56 "mfcr %0;" in paste_last()
64 #define PPC_INST_COPY __COPY(0, 0, 0)
65 #define PPC_INST_COPY_FIRST __COPY(0, 0, 1)
[all …]
/openbmc/u-boot/post/lib_powerpc/
H A Dcpu_asm.h9 #define BIT_C 0x00000001
11 #define OP_BLR 0x4e800020
12 #define OP_EXTSB 0x7c000774
13 #define OP_EXTSH 0x7c000734
14 #define OP_NEG 0x7c0000d0
15 #define OP_CNTLZW 0x7c000034
16 #define OP_ADD 0x7c000214
17 #define OP_ADDC 0x7c000014
18 #define OP_ADDME 0x7c0001d4
19 #define OP_ADDZE 0x7c000194
[all …]
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dsama5d2.h15 #define ATMEL_ID_FIQ 0 /* FIQ Interrupt ID */
21 #define ATMEL_ID_XDMAC0 6 /* DMA Controller 0 */
44 #define ATMEL_ID_TWIHS0 29 /* Two-wire Interface 0 */
46 #define ATMEL_ID_SDMMC0 31 /* Secure Data Memory Card Controller 0 */
48 #define ATMEL_ID_SPI0 33 /* Serial Peripheral Interface 0 */
50 #define ATMEL_ID_TC0 35 /* Timer Counter 0 (ch.0,1,2) */
53 #define ATMEL_ID_PWM 38 /* PWMController0 (ch. 0,1,2,3) */
58 #define ATMEL_ID_SSC0 43 /* Serial Synchronous Controller 0 */
69 #define ATMEL_ID_I2SC0 54 /* Inter-IC Sound Controller 0 */
71 #define ATMEL_ID_CAN0_INT0 56 /* MCAN 0 Interrupt0 */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,omap-remoteproc.yaml235 reg = <0x98000000 0x800000>;
244 ti,bootreg = <&scm_conf 0x304 0>;
250 clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
251 resets = <&prm_tesla 0>, <&prm_tesla 1>;
268 reg = <0 0x95800000 0 0x3800000>;
280 reg = <0x55020000 0x10000>;
287 clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
305 reg = <0x0 0x99000000 0x0 0x4000000>;
317 reg = <0x40800000 0x48000>,
318 <0x40e00000 0x8000>,
[all …]
/openbmc/u-boot/board/renesas/sh7785lcr/
H A Dlowlevel_init.S125 * 0 0xa0000000 0x00000000 1 64M 0 0
126 * 1 0xa4000000 0x04000000 1 16M 0 0
127 * 2 0xa6000000 0x08000000 1 16M 0 0
128 * 9 0x88000000 0x48000000 1 128M 1 1
129 * 10 0x90000000 0x50000000 1 128M 1 1
130 * 11 0x98000000 0x58000000 1 128M 1 1
131 * 13 0xa8000000 0x48000000 1 128M 0 0
132 * 14 0xb0000000 0x50000000 1 128M 0 0
133 * 15 0xb8000000 0x58000000 1 128M 0 0
168 PXCR_D: .word 0x0000
[all …]
/openbmc/u-boot/board/renesas/sh7752evb/
H A Dsh7752evb.c19 return 0; in checkboard()
28 writew(0x0000, &gpio->pacr); /* GETHER */ in init_gpio()
29 writew(0x0001, &gpio->pbcr); /* INTC */ in init_gpio()
30 writew(0x0000, &gpio->pccr); /* PWMU, INTC */ in init_gpio()
31 writew(0xeaff, &gpio->pecr); /* GPIO */ in init_gpio()
32 writew(0x0000, &gpio->pfcr); /* WDT */ in init_gpio()
33 writew(0x0000, &gpio->phcr); /* SPI1 */ in init_gpio()
34 writew(0x0000, &gpio->picr); /* SDHI */ in init_gpio()
35 writew(0x0003, &gpio->pkcr); /* SerMux */ in init_gpio()
36 writew(0x0000, &gpio->plcr); /* SerMux */ in init_gpio()
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8dxl-evk.dts27 reg = <0x00000000 0x80000000 0 0x40000000>;
39 * reg = <0 0x96000000 0 0x2000000>;
48 size = <0 0x14000000>;
49 alloc-ranges = <0 0x98000000 0 0x14000000>;
54 mux3_en: regulator-0 {
78 gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
119 pinctrl-0 = <&pinctrl_eqos>;
129 #size-cells = <0>;
131 ethphy0: ethernet-phy@0 {
133 reg = <0>;
[all …]
/openbmc/u-boot/board/renesas/sh7753evb/
H A Dsh7753evb.c19 return 0; in checkboard()
28 writew(0x0000, &gpio->pacr); /* GETHER */ in init_gpio()
29 writew(0x0001, &gpio->pbcr); /* INTC */ in init_gpio()
30 writew(0x0000, &gpio->pccr); /* PWMU, INTC */ in init_gpio()
31 writew(0x0000, &gpio->pdcr); /* SPI0 */ in init_gpio()
32 writew(0xeaff, &gpio->pecr); /* GPIO */ in init_gpio()
33 writew(0x0000, &gpio->pfcr); /* WDT */ in init_gpio()
34 writew(0x0004, &gpio->pgcr); /* SPI0, GETHER MDIO gate(PTG1) */ in init_gpio()
35 writew(0x0000, &gpio->phcr); /* SPI1 */ in init_gpio()
36 writew(0x0000, &gpio->picr); /* SDHI */ in init_gpio()
[all …]
/openbmc/linux/Documentation/arch/xtensa/
H A Dmmu.rst16 - RASID is 0x04030201 (reset state).
28 After step 2, we jump to virtual address in the range 0x40000000..0x5fffffff
29 or 0x00000000..0x1fffffff, depending on whether the kernel was loaded below
30 0x40000000 or above. That address corresponds to next instruction to execute
32 The scheme below assumes that the kernel is loaded below 0x40000000.
49 The default location of IO peripherals is above 0xf0000000. This may be changed
75 | Userspace | 0x00000000 TASK_SIZE
76 +------------------+ 0x40000000
78 | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE
80 | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE
[all …]
/openbmc/qemu/hw/openrisc/
H A Dopenrisc_sim.c41 #define KERNEL_LOAD_ADDR 0x100
81 [OR1KSIM_DRAM] = { 0x00000000, 0 },
82 [OR1KSIM_UART] = { 0x90000000, 0x100 },
83 [OR1KSIM_ETHOC] = { 0x92000000, 0x800 },
84 [OR1KSIM_OMPIC] = { 0x98000000, OR1KSIM_CPUS_MAX * 8 },
125 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x1); in openrisc_create_fdt()
126 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x1); in openrisc_create_fdt()
137 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); in openrisc_create_fdt()
138 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); in openrisc_create_fdt()
140 for (cpu = 0; cpu < num_cpus; cpu++) { in openrisc_create_fdt()
[all …]
/openbmc/u-boot/board/renesas/sh7757lcr/
H A Dsh7757lcr.c19 return 0; in checkboard()
28 writel(graofst | 0x20000f00, &gctrl->gracr3); in init_gctrl()
37 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); in init_pcie_bridge_from_spi()
56 return 0; in init_pcie_bridge_from_spi()
68 if (!(readw(&pciebrg->ctrl_h8s) & 0x0001)) in init_pcie_bridge()
86 if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff && in init_pcie_bridge()
87 data[3] == 0xff) { in init_pcie_bridge()
93 writew(0xa501, &pciebrg->ctrl_h8s); /* reset */ in init_pcie_bridge()
94 writew(0x0000, &pciebrg->cp_ctrl); in init_pcie_bridge()
95 writew(0x0000, &pciebrg->cp_addr); in init_pcie_bridge()
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dmakalu.dts18 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
48 reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
54 cell-index = <0>;
55 dcr-reg = <0x0c0 0x009>;
56 #address-cells = <0>;
[all …]

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