Lines Matching +full:0 +full:x98000000
17 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
22 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
26 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
62 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */
63 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */
68 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
70 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
77 #define CONFIG_SYS_CCSRBAR 0xffe00000
90 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
92 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
99 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
104 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
105 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
106 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
107 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
108 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
109 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
110 #define CONFIG_SYS_DDR_MODE_1 0x00480432
111 #define CONFIG_SYS_DDR_MODE_2 0x00000000
112 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
113 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
114 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
115 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
116 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
117 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
118 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
120 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
121 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
122 #define CONFIG_SYS_DDR_SBE 0x00010000
134 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
135 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
136 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
137 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
140 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
143 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable
144 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
145 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
146 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
147 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
148 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
154 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
156 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
162 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
163 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
168 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
170 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
192 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
194 #define PIXIS_BASE_PHYS 0xfffdf0000ull
200 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
202 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
203 #define PIXIS_VER 0x1 /* Board version at offset 1 */
204 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
205 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */
206 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
207 #define PIXIS_PWR 0x5 /* PIXIS Power status register */
208 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */
209 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
210 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
211 #define PIXIS_VCTL 0x10 /* VELA Control Register */
212 #define PIXIS_VSTAT 0x11 /* VELA Status Register */
213 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
214 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
215 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
216 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
217 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */
218 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
219 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */
220 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */
221 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */
222 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */
223 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */
224 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
225 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
226 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
227 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */
228 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */
229 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */
230 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */
231 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */
232 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */
233 #define PIXIS_VWATCH 0x24 /* Watchdog Register */
234 #define PIXIS_LED 0x25 /* LED Register */
236 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */
239 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
240 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
241 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e
244 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
245 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
255 #define CONFIG_SYS_NAND_BASE 0xffa00000
257 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
262 #define CONFIG_SYS_NAND_BASE 0xfff00000
264 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
270 CONFIG_SYS_NAND_BASE + 0x40000, \
271 CONFIG_SYS_NAND_BASE + 0x80000, \
272 CONFIG_SYS_NAND_BASE + 0xC0000}
278 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
279 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
283 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
284 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
285 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
294 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
309 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
316 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
324 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
337 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
345 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
346 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
354 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
355 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
357 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
358 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
359 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
368 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
374 * Memory space is mapped 1-1, but I/O space must start from 0.
377 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
379 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
380 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
382 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
383 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
385 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
386 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
387 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
389 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull
391 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
393 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
397 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
399 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
400 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
402 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
403 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
405 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */
406 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
407 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
409 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull
411 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
413 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
417 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
419 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
420 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
422 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
423 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
425 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */
426 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
427 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
429 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull
431 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
433 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
437 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
439 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
440 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
442 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
443 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
445 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
446 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
447 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
449 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull
451 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
453 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
477 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
506 #define SGMII_RISER_PHY_OFFSET 0x1c
509 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */
514 #define TSEC1_PHYIDX 0
515 #define TSEC3_PHYIDX 0
527 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
528 #define CONFIG_ENV_OFFSET 0xF0000
529 #define CONFIG_ENV_SECT_SIZE 0x10000
532 #define CONFIG_ENV_SIZE 0x2000
533 #define CONFIG_SYS_MMC_ENV_DEV 0
535 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
536 #define CONFIG_ENV_SIZE 0x2000
540 #define CONFIG_ENV_SIZE 0x2000
541 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
567 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
608 "netdev=eth0\0" \
609 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
620 " $filesize\0" \
621 "consoledev=ttyS0\0" \
622 "ramdiskaddr=2000000\0" \
623 "ramdiskfile=8536ds/ramdisk.uboot\0" \
624 "fdtaddr=1e00000\0" \
625 "fdtfile=8536ds/mpc8536ds.dtb\0" \
626 "bdev=sda3\0" \
627 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"