1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2a47a12beSStefan Roese /* 3a47a12beSStefan Roese * (C) Copyright 2002 4a47a12beSStefan Roese * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5a47a12beSStefan Roese */ 6a47a12beSStefan Roese #ifndef _CPU_ASM_H 7a47a12beSStefan Roese #define _CPU_ASM_H 8a47a12beSStefan Roese 9a47a12beSStefan Roese #define BIT_C 0x00000001 10a47a12beSStefan Roese 11a47a12beSStefan Roese #define OP_BLR 0x4e800020 12a47a12beSStefan Roese #define OP_EXTSB 0x7c000774 13a47a12beSStefan Roese #define OP_EXTSH 0x7c000734 14a47a12beSStefan Roese #define OP_NEG 0x7c0000d0 15a47a12beSStefan Roese #define OP_CNTLZW 0x7c000034 16a47a12beSStefan Roese #define OP_ADD 0x7c000214 17a47a12beSStefan Roese #define OP_ADDC 0x7c000014 18a47a12beSStefan Roese #define OP_ADDME 0x7c0001d4 19a47a12beSStefan Roese #define OP_ADDZE 0x7c000194 20a47a12beSStefan Roese #define OP_ADDE 0x7c000114 21a47a12beSStefan Roese #define OP_ADDI 0x38000000 22a47a12beSStefan Roese #define OP_SUBF 0x7c000050 23a47a12beSStefan Roese #define OP_SUBFC 0x7c000010 24a47a12beSStefan Roese #define OP_SUBFE 0x7c000110 25a47a12beSStefan Roese #define OP_SUBFME 0x7c0001d0 26a47a12beSStefan Roese #define OP_SUBFZE 0x7c000190 27a47a12beSStefan Roese #define OP_MFCR 0x7c000026 28a47a12beSStefan Roese #define OP_MTCR 0x7c0ff120 29a47a12beSStefan Roese #define OP_MFXER 0x7c0102a6 30a47a12beSStefan Roese #define OP_MTXER 0x7c0103a6 31a47a12beSStefan Roese #define OP_MCRXR 0x7c000400 32a47a12beSStefan Roese #define OP_MCRF 0x4c000000 33a47a12beSStefan Roese #define OP_CRAND 0x4c000202 34a47a12beSStefan Roese #define OP_CRANDC 0x4c000102 35a47a12beSStefan Roese #define OP_CROR 0x4c000382 36a47a12beSStefan Roese #define OP_CRORC 0x4c000342 37a47a12beSStefan Roese #define OP_CRXOR 0x4c000182 38a47a12beSStefan Roese #define OP_CRNAND 0x4c0001c2 39a47a12beSStefan Roese #define OP_CRNOR 0x4c000042 40a47a12beSStefan Roese #define OP_CREQV 0x4c000242 41a47a12beSStefan Roese #define OP_CMPW 0x7c000000 42a47a12beSStefan Roese #define OP_CMPLW 0x7c000040 43a47a12beSStefan Roese #define OP_CMPWI 0x2c000000 44a47a12beSStefan Roese #define OP_CMPLWI 0x28000000 45a47a12beSStefan Roese #define OP_MULLW 0x7c0001d6 46a47a12beSStefan Roese #define OP_MULHW 0x7c000096 47a47a12beSStefan Roese #define OP_MULHWU 0x7c000016 48a47a12beSStefan Roese #define OP_DIVW 0x7c0003d6 49a47a12beSStefan Roese #define OP_DIVWU 0x7c000396 50a47a12beSStefan Roese #define OP_OR 0x7c000378 51a47a12beSStefan Roese #define OP_ORC 0x7c000338 52a47a12beSStefan Roese #define OP_XOR 0x7c000278 53a47a12beSStefan Roese #define OP_NAND 0x7c0003b8 54a47a12beSStefan Roese #define OP_NOR 0x7c0000f8 55a47a12beSStefan Roese #define OP_EQV 0x7c000238 56a47a12beSStefan Roese #define OP_SLW 0x7c000030 57a47a12beSStefan Roese #define OP_SRW 0x7c000430 58a47a12beSStefan Roese #define OP_SRAW 0x7c000630 59a47a12beSStefan Roese #define OP_ORI 0x60000000 60a47a12beSStefan Roese #define OP_ORIS 0x64000000 61a47a12beSStefan Roese #define OP_XORI 0x68000000 62a47a12beSStefan Roese #define OP_XORIS 0x6c000000 63a47a12beSStefan Roese #define OP_ANDI_ 0x70000000 64a47a12beSStefan Roese #define OP_ANDIS_ 0x74000000 65a47a12beSStefan Roese #define OP_SRAWI 0x7c000670 66a47a12beSStefan Roese #define OP_RLWINM 0x54000000 67a47a12beSStefan Roese #define OP_RLWNM 0x5c000000 68a47a12beSStefan Roese #define OP_RLWIMI 0x50000000 69a47a12beSStefan Roese #define OP_LWZ 0x80000000 70a47a12beSStefan Roese #define OP_LHZ 0xa0000000 71a47a12beSStefan Roese #define OP_LHA 0xa8000000 72a47a12beSStefan Roese #define OP_LBZ 0x88000000 73a47a12beSStefan Roese #define OP_LWZU 0x84000000 74a47a12beSStefan Roese #define OP_LHZU 0xa4000000 75a47a12beSStefan Roese #define OP_LHAU 0xac000000 76a47a12beSStefan Roese #define OP_LBZU 0x8c000000 77a47a12beSStefan Roese #define OP_LWZX 0x7c00002e 78a47a12beSStefan Roese #define OP_LHZX 0x7c00022e 79a47a12beSStefan Roese #define OP_LHAX 0x7c0002ae 80a47a12beSStefan Roese #define OP_LBZX 0x7c0000ae 81a47a12beSStefan Roese #define OP_LWZUX 0x7c00006e 82a47a12beSStefan Roese #define OP_LHZUX 0x7c00026e 83a47a12beSStefan Roese #define OP_LHAUX 0x7c0002ee 84a47a12beSStefan Roese #define OP_LBZUX 0x7c0000ee 85a47a12beSStefan Roese #define OP_STW 0x90000000 86a47a12beSStefan Roese #define OP_STH 0xb0000000 87a47a12beSStefan Roese #define OP_STB 0x98000000 88a47a12beSStefan Roese #define OP_STWU 0x94000000 89a47a12beSStefan Roese #define OP_STHU 0xb4000000 90a47a12beSStefan Roese #define OP_STBU 0x9c000000 91a47a12beSStefan Roese #define OP_STWX 0x7c00012e 92a47a12beSStefan Roese #define OP_STHX 0x7c00032e 93a47a12beSStefan Roese #define OP_STBX 0x7c0001ae 94a47a12beSStefan Roese #define OP_STWUX 0x7c00016e 95a47a12beSStefan Roese #define OP_STHUX 0x7c00036e 96a47a12beSStefan Roese #define OP_STBUX 0x7c0001ee 97a47a12beSStefan Roese #define OP_B 0x48000000 98a47a12beSStefan Roese #define OP_BL 0x48000001 99a47a12beSStefan Roese #define OP_BC 0x40000000 100a47a12beSStefan Roese #define OP_BCL 0x40000001 101a47a12beSStefan Roese #define OP_MTLR 0x7c0803a6 102a47a12beSStefan Roese #define OP_MFLR 0x7c0802a6 103a47a12beSStefan Roese #define OP_MTCTR 0x7c0903a6 104a47a12beSStefan Roese #define OP_MFCTR 0x7c0902a6 105a47a12beSStefan Roese #define OP_LMW 0xb8000000 106a47a12beSStefan Roese #define OP_STMW 0xbc000000 107a47a12beSStefan Roese #define OP_LSWI 0x7c0004aa 108a47a12beSStefan Roese #define OP_LSWX 0x7c00042a 109a47a12beSStefan Roese #define OP_STSWI 0x7c0005aa 110a47a12beSStefan Roese #define OP_STSWX 0x7c00052a 111a47a12beSStefan Roese 112a47a12beSStefan Roese #define ASM_0(opcode) (opcode) 113a47a12beSStefan Roese #define ASM_1(opcode, rd) ((opcode) + \ 114a47a12beSStefan Roese ((rd) << 21)) 115a47a12beSStefan Roese #define ASM_1C(opcode, cr) ((opcode) + \ 116a47a12beSStefan Roese ((cr) << 23)) 117a47a12beSStefan Roese #define ASM_11(opcode, rd, rs) ((opcode) + \ 118a47a12beSStefan Roese ((rd) << 21) + \ 119a47a12beSStefan Roese ((rs) << 16)) 120a47a12beSStefan Roese #define ASM_11C(opcode, cd, cs) ((opcode) + \ 121a47a12beSStefan Roese ((cd) << 23) + \ 122a47a12beSStefan Roese ((cs) << 18)) 123a47a12beSStefan Roese #define ASM_11X(opcode, rd, rs) ((opcode) + \ 124a47a12beSStefan Roese ((rs) << 21) + \ 125a47a12beSStefan Roese ((rd) << 16)) 126a47a12beSStefan Roese #define ASM_11I(opcode, rd, rs, simm) ((opcode) + \ 127a47a12beSStefan Roese ((rd) << 21) + \ 128a47a12beSStefan Roese ((rs) << 16) + \ 129a47a12beSStefan Roese ((simm) & 0xffff)) 130a47a12beSStefan Roese #define ASM_11IF(opcode, rd, rs, simm) ((opcode) + \ 131a47a12beSStefan Roese ((rd) << 21) + \ 132a47a12beSStefan Roese ((rs) << 16) + \ 133a47a12beSStefan Roese ((simm) << 11)) 134a47a12beSStefan Roese #define ASM_11S(opcode, rd, rs, sh) ((opcode) + \ 135a47a12beSStefan Roese ((rs) << 21) + \ 136a47a12beSStefan Roese ((rd) << 16) + \ 137a47a12beSStefan Roese ((sh) << 11)) 138a47a12beSStefan Roese #define ASM_11IX(opcode, rd, rs, imm) ((opcode) + \ 139a47a12beSStefan Roese ((rs) << 21) + \ 140a47a12beSStefan Roese ((rd) << 16) + \ 141a47a12beSStefan Roese ((imm) & 0xffff)) 142a47a12beSStefan Roese #define ASM_12(opcode, rd, rs1, rs2) ((opcode) + \ 143a47a12beSStefan Roese ((rd) << 21) + \ 144a47a12beSStefan Roese ((rs1) << 16) + \ 145a47a12beSStefan Roese ((rs2) << 11)) 146a47a12beSStefan Roese #define ASM_12F(opcode, fd, fs1, fs2) ((opcode) + \ 147a47a12beSStefan Roese ((fd) << 21) + \ 148a47a12beSStefan Roese ((fs1) << 16) + \ 149a47a12beSStefan Roese ((fs2) << 11)) 150a47a12beSStefan Roese #define ASM_12X(opcode, rd, rs1, rs2) ((opcode) + \ 151a47a12beSStefan Roese ((rs1) << 21) + \ 152a47a12beSStefan Roese ((rd) << 16) + \ 153a47a12beSStefan Roese ((rs2) << 11)) 154a47a12beSStefan Roese #define ASM_2C(opcode, cr, rs1, rs2) ((opcode) + \ 155a47a12beSStefan Roese ((cr) << 23) + \ 156a47a12beSStefan Roese ((rs1) << 16) + \ 157a47a12beSStefan Roese ((rs2) << 11)) 158a47a12beSStefan Roese #define ASM_1IC(opcode, cr, rs, imm) ((opcode) + \ 159a47a12beSStefan Roese ((cr) << 23) + \ 160a47a12beSStefan Roese ((rs) << 16) + \ 161a47a12beSStefan Roese ((imm) & 0xffff)) 162a47a12beSStefan Roese #define ASM_122(opcode, rd, rs1, rs2, imm1, imm2) \ 163a47a12beSStefan Roese ((opcode) + \ 164a47a12beSStefan Roese ((rs1) << 21) + \ 165a47a12beSStefan Roese ((rd) << 16) + \ 166a47a12beSStefan Roese ((rs2) << 11) + \ 167a47a12beSStefan Roese ((imm1) << 6) + \ 168a47a12beSStefan Roese ((imm2) << 1)) 169a47a12beSStefan Roese #define ASM_113(opcode, rd, rs, imm1, imm2, imm3) \ 170a47a12beSStefan Roese ((opcode) + \ 171a47a12beSStefan Roese ((rs) << 21) + \ 172a47a12beSStefan Roese ((rd) << 16) + \ 173a47a12beSStefan Roese ((imm1) << 11) + \ 174a47a12beSStefan Roese ((imm2) << 6) + \ 175a47a12beSStefan Roese ((imm3) << 1)) 176a47a12beSStefan Roese #define ASM_1O(opcode, off) ((opcode) + (off)) 177a47a12beSStefan Roese #define ASM_3O(opcode, bo, bi, off) ((opcode) + \ 178a47a12beSStefan Roese ((bo) << 21) + \ 179a47a12beSStefan Roese ((bi) << 16) + \ 180a47a12beSStefan Roese (off)) 181a47a12beSStefan Roese 182a47a12beSStefan Roese #define ASM_ADDI(rd, rs, simm) ASM_11I(OP_ADDI, rd, rs, simm) 183a47a12beSStefan Roese #define ASM_BLR ASM_0(OP_BLR) 184a47a12beSStefan Roese #define ASM_STW(rd, rs, simm) ASM_11I(OP_STW, rd, rs, simm) 185a47a12beSStefan Roese #define ASM_LWZ(rd, rs, simm) ASM_11I(OP_LWZ, rd, rs, simm) 186a47a12beSStefan Roese #define ASM_MFCR(rd) ASM_1(OP_MFCR, rd) 187a47a12beSStefan Roese #define ASM_MTCR(rd) ASM_1(OP_MTCR, rd) 188a47a12beSStefan Roese #define ASM_MFXER(rd) ASM_1(OP_MFXER, rd) 189a47a12beSStefan Roese #define ASM_MTXER(rd) ASM_1(OP_MTXER, rd) 190a47a12beSStefan Roese #define ASM_MFCTR(rd) ASM_1(OP_MFCTR, rd) 191a47a12beSStefan Roese #define ASM_MTCTR(rd) ASM_1(OP_MTCTR, rd) 192a47a12beSStefan Roese #define ASM_MCRXR(cr) ASM_1C(OP_MCRXR, cr) 193a47a12beSStefan Roese #define ASM_MCRF(cd, cs) ASM_11C(OP_MCRF, cd, cs) 194a47a12beSStefan Roese #define ASM_B(off) ASM_1O(OP_B, off) 195a47a12beSStefan Roese #define ASM_BL(off) ASM_1O(OP_BL, off) 196a47a12beSStefan Roese #define ASM_MFLR(rd) ASM_1(OP_MFLR, rd) 197a47a12beSStefan Roese #define ASM_MTLR(rd) ASM_1(OP_MTLR, rd) 198a47a12beSStefan Roese #define ASM_LI(rd, imm) ASM_ADDI(rd, 0, imm) 199a47a12beSStefan Roese #define ASM_LMW(rd, rs, simm) ASM_11I(OP_LMW, rd, rs, simm) 200a47a12beSStefan Roese #define ASM_STMW(rd, rs, simm) ASM_11I(OP_STMW, rd, rs, simm) 201a47a12beSStefan Roese #define ASM_LSWI(rd, rs, simm) ASM_11IF(OP_LSWI, rd, rs, simm) 202a47a12beSStefan Roese #define ASM_LSWX(rd, rs1, rs2) ASM_12(OP_LSWX, rd, rs1, rs2) 203a47a12beSStefan Roese #define ASM_STSWI(rd, rs, simm) ASM_11IF(OP_STSWI, rd, rs, simm) 204a47a12beSStefan Roese #define ASM_STSWX(rd, rs1, rs2) ASM_12(OP_STSWX, rd, rs1, rs2) 205a47a12beSStefan Roese 206a47a12beSStefan Roese 207a47a12beSStefan Roese #endif /* _CPU_ASM_H */ 208