19 	return 0;  in checkboard()
28 	writel(graofst | 0x20000f00, &gctrl->gracr3);  in init_gctrl()
37 	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);  in init_pcie_bridge_from_spi()
56 	return 0;  in init_pcie_bridge_from_spi()
68 	if (!(readw(&pciebrg->ctrl_h8s) & 0x0001))  in init_pcie_bridge()
86 	if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff &&  in init_pcie_bridge()
87 	    data[3] == 0xff) {  in init_pcie_bridge()
93 	writew(0xa501, &pciebrg->ctrl_h8s);	/* reset */  in init_pcie_bridge()
94 	writew(0x0000, &pciebrg->cp_ctrl);  in init_pcie_bridge()
95 	writew(0x0000, &pciebrg->cp_addr);  in init_pcie_bridge()
97 	for (i = 0; i < pcie_size; i += 2) {  in init_pcie_bridge()
102 	writew(0xa500, &pciebrg->ctrl_h8s);	/* start */  in init_pcie_bridge()
104 		writel(0x00000001, &pcie_setup->pbictl3);  in init_pcie_bridge()
117 	writew(0x0100, &phy->reset);		/* set reset */  in init_usb_phy()
119 	writew(0x0002, &phy->portsel);  in init_usb_phy()
120 	writel(0x0001, &port->port1sel);	/* port1 = Host */  in init_usb_phy()
121 	writew(0x0111, &phy->reset);		/* clear reset */  in init_usb_phy()
123 	writew(0x4000, &common0->suspmode);  in init_usb_phy()
124 	writew(0x4000, &common1->suspmode);  in init_usb_phy()
127 	writel(0x00000000, &align->ehcidatac);  in init_usb_phy()
128 	writel(0x00000000, &align->ohcidatac);  in init_usb_phy()
145 	val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];  in set_mac_to_sh_eth_register()
164 	val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];  in set_mac_to_sh_giga_eth_register()
172  * Area 0(phys 0x00000000), so we have to map it.
176  * 0	0xa0000000	0x40000000	1	128M	0	1
177  * 1	0xa8000000	0x48000000	1	128M	0	1
178  * 2	0xb0000000	0x50000000	1	128M	0	1
179  * 3	0xb8000000	0x58000000	1	128M	0	1
180  * 4	0x80000000	0x40000000	1	128M	1	1
181  * 5	0x88000000	0x48000000	1	128M	1	1
182  * 6	0x90000000	0x50000000	1	128M	1	1
183  * 7	0x98000000	0x58000000	1	128M	1	1
190 	writel(0x00000004, &mmu->mmucr);  in set_pmb_on_board_init()
193 	writel(0, PMB_ADDR_BASE(0));  in set_pmb_on_board_init()
194 	writel(0, PMB_DATA_BASE(0));  in set_pmb_on_board_init()
196 	/* add PMB for SDRAM(0x40000000 - 0x47ffffff) */  in set_pmb_on_board_init()
198 	writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));  in set_pmb_on_board_init()
199 	writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));  in set_pmb_on_board_init()
200 	writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));  in set_pmb_on_board_init()
201 	writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));  in set_pmb_on_board_init()
202 	writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));  in set_pmb_on_board_init()
203 	writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));  in set_pmb_on_board_init()
204 	writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));  in set_pmb_on_board_init()
205 	writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));  in set_pmb_on_board_init()
206 	writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));  in set_pmb_on_board_init()
207 	writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));  in set_pmb_on_board_init()
208 	writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));  in set_pmb_on_board_init()
209 	writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));  in set_pmb_on_board_init()
219 	writel(0x00030000, &gether->gbecont);  in board_init()
224 	return 0;  in board_init()
237 	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);  in get_sh_eth_mac_raw()
251 	return 0;  in get_sh_eth_mac_raw()
258 	mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00;	/* terminate */  in get_sh_eth_mac()
260 	return 0;  in get_sh_eth_mac()
278 	for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) {  in init_ethernet_mac()
280 		if (i == 0)  in init_ethernet_mac()
291 	for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) {  in init_ethernet_mac()
307 	writel(0x00000ff2, &pcie_setup->ladmsk0);  in init_pcie()
308 	writel(0x00000001, &pcie_setup->barmap);  in init_pcie()
309 	writel(0xffcaa000, &pcie_setup->lad0);  in init_pcie()
310 	writel(0x00030000, &pcie_sysbus->endictl0);  in init_pcie()
311 	writel(0x00000003, &pcie_sysbus->endictl1);  in init_pcie()
312 	writel(0x00000004, &pcie_setup->pbictl2);  in init_pcie()
322 	 *  to 0.  in finish_spiboot()
324 	writel(0x00000000, &gctrl->spibootcan);  in finish_spiboot()
334 	return 0;  in board_late_init()
342 	writel(0xfedcba98, &gctrl->wprotect);  in do_sh_g200()
344 	writel(graofst | 0xa0000f00, &gctrl->gracr3);  in do_sh_g200()
346 	return 0;  in do_sh_g200()
372 		for (i = 0; i < 4; i++) {  in do_write_mac()
380 		return 0;  in do_write_mac()
384 	memset(mac_string, 0xff, sizeof(mac_string));  in do_write_mac()
389 	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);  in do_write_mac()
413 	return 0;  in do_write_mac()