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/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
H A Dtable.c7 0x800, 0x80040000,
8 0x804, 0x00000003,
9 0x808, 0x0000fc00,
10 0x80c, 0x0000000a,
11 0x810, 0x10005388,
12 0x814, 0x020c3d10,
13 0x818, 0x02200385,
14 0x81c, 0x00000000,
15 0x820, 0x01000100,
16 0x824, 0x00390004,
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/
H A Dtable.c7 0x024, 0x0011800f,
8 0x028, 0x00ffdb83,
9 0x800, 0x80040002,
10 0x804, 0x00000003,
11 0x808, 0x0000fc00,
12 0x80c, 0x0000000a,
13 0x810, 0x10000330,
14 0x814, 0x020c3d10,
15 0x818, 0x02200385,
16 0x81c, 0x00000000,
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
H A Dtable.c9 0x024, 0x0011800d,
10 0x028, 0x00ffdb83,
11 0x014, 0x088ba955,
12 0x010, 0x49022b03,
13 0x800, 0x80040002,
14 0x804, 0x00000003,
15 0x808, 0x0000fc00,
16 0x80c, 0x0000000a,
17 0x810, 0x80706388,
18 0x814, 0x020c3d10,
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/
H A Dtable.c7 0x024, 0x0011800f,
8 0x028, 0x00ffdb83,
9 0x800, 0x80040002,
10 0x804, 0x00000003,
11 0x808, 0x0000fc00,
12 0x80c, 0x0000000a,
13 0x810, 0x10005388,
14 0x814, 0x020c3d10,
15 0x818, 0x02200385,
16 0x81c, 0x00000000,
[all …]
/openbmc/linux/drivers/staging/rtl8723bs/hal/
H A Dodm_reg.h16 #define ODM_BB_RESET 0x002
17 #define ODM_DUMMY 0x4fe
18 #define RF_T_METER_OLD 0x24
19 #define RF_T_METER_NEW 0x42
21 #define ODM_EDCA_VO_PARAM 0x500
22 #define ODM_EDCA_VI_PARAM 0x504
23 #define ODM_EDCA_BE_PARAM 0x508
24 #define ODM_EDCA_BK_PARAM 0x50C
25 #define ODM_TXPAUSE 0x522
28 #define ODM_FPGA_PHY0_PAGE8 0x800
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/
H A Dbcm4908_enet.h5 #define ENET_CONTROL 0x000
6 #define ENET_MIB_CTRL 0x004
7 #define ENET_MIB_CTRL_CLR_MIB 0x00000001
8 #define ENET_RX_ERR_MASK 0x008
9 #define ENET_MIB_MAX_PKT_SIZE 0x00C
10 #define ENET_MIB_MAX_PKT_SIZE_VAL 0x00003fff
11 #define ENET_DIAG_OUT 0x01c
12 #define ENET_ENABLE_DROP_PKT 0x020
13 #define ENET_IRQ_ENABLE 0x024
14 #define ENET_IRQ_ENABLE_OVFL 0x00000001
[all …]
/openbmc/linux/drivers/staging/rtl8192u/
H A Dr819xU_phyreg.h5 #define RF_DATA 0x1d4 /* FW will write RF data in the register.*/
8 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */
9 #define rFPGA0_TxGainStage 0x80c
10 #define rFPGA0_XA_HSSIParameter1 0x820
11 #define rFPGA0_XA_HSSIParameter2 0x824
12 #define rFPGA0_XB_HSSIParameter1 0x828
13 #define rFPGA0_XB_HSSIParameter2 0x82c
14 #define rFPGA0_XC_HSSIParameter1 0x830
15 #define rFPGA0_XC_HSSIParameter2 0x834
16 #define rFPGA0_XD_HSSIParameter1 0x838
[all …]
/openbmc/linux/include/dt-bindings/pinctrl/
H A Dam33xx.h18 #define SLEWCTRL_FAST 0
30 #define PIN_OUTPUT_PULLDOWN 0
43 #define AM335X_PIN_OFFSET_MIN 0x0800U
45 #define AM335X_PIN_GPMC_AD0 0x800
46 #define AM335X_PIN_GPMC_AD1 0x804
47 #define AM335X_PIN_GPMC_AD2 0x808
48 #define AM335X_PIN_GPMC_AD3 0x80c
49 #define AM335X_PIN_GPMC_AD4 0x810
50 #define AM335X_PIN_GPMC_AD5 0x814
51 #define AM335X_PIN_GPMC_AD6 0x818
[all …]
/openbmc/u-boot/board/freescale/mx6sllevk/
H A Dplugin.S11 ldr r1, =0x00080000
12 str r1, [r0, #0x550]
13 ldr r1, =0x00000000
14 str r1, [r0, #0x534]
15 ldr r1, =0x00000030
16 str r1, [r0, #0x2AC]
17 str r1, [r0, #0x548]
18 str r1, [r0, #0x52C]
19 ldr r1, =0x00020000
20 str r1, [r0, #0x530]
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra20-vi.yaml15 pattern: "^vi@[0-9a-f]+$"
83 port@0:
89 "^csi@[0-9a-f]+$":
125 #size-cells = <0>;
128 reg = <0x48>;
141 reg = <0x54080000 0x00040000>;
151 #size-cells = <0>;
152 port@0 {
153 reg = <0>;
169 #size-cells = <0>;
[all …]
H A Dnvidia,tegra20-host1x.yaml175 use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
202 - description: host1x syncpoint interrupt 0
226 use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
240 reg = <0x50000000 0x00024000>;
241 interrupts = <0 65 0x04>, /* mpcore syncpt */
242 <0 67 0x04>; /* mpcore general */
252 ranges = <0x54000000 0x54000000 0x04000000>;
256 reg = <0x54040000 0x00040000>;
257 interrupts = <0 68 0x04>;
265 reg = <0x54080000 0x00040000>;
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8822b.h13 u8 res4[4]; /* 0xd0 */
15 u8 res5[0x1e];
17 u8 serial[0x0b]; /* 0xf5 */
18 u8 vid; /* 0x100 */
22 u8 mac_addr[ETH_ALEN]; /* 0x107 */
24 u8 vendor_name[0x07];
26 u8 device_name[0x14];
27 u8 res11[0xcf];
28 u8 package_type; /* 0x1fb */
29 u8 res12[0x4];
[all …]
H A Drtw8821c.h13 u8 res4[4]; /* 0xd0 */
15 u8 res5[0x1e];
17 u8 serial[0x0b]; /* 0xf5 */
18 u8 vid; /* 0x100 */
22 u8 mac_addr[ETH_ALEN]; /* 0x107 */
24 u8 vendor_name[0x07];
26 u8 device_name[0x14];
27 u8 res11[0xcf];
28 u8 package_type; /* 0x1fb */
29 u8 res12[0x4];
[all …]
/openbmc/u-boot/board/freescale/mx7ulp_evk/
H A Dplugin.S9 ldr r2, =0x403f0000
10 ldr r3, =0x00000000
11 str r3, [r2, #0xdc]
13 ldr r2, =0x403e0000
14 ldr r3, =0x01000020
15 str r3, [r2, #0x40]
16 ldr r3, =0x01000000
17 str r3, [r2, #0x500]
18 ldr r3, =0x80808080
19 str r3, [r2, #0x50c]
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dam335x-evmsk.dts30 cpu@0 {
37 reg = <0x80000000 0x10000000>; /* 256 MB */
40 vbat: fixedregulator@0 {
56 pinctrl-0 = <&wl12xx_gpio>;
61 gpio = <&gpio1 29 0>;
79 pinctrl-0 = <&user_leds_s0>;
110 gpio_buttons: gpio_buttons@0 {
115 linux,code = <0x100>;
121 linux,code = <0x101>;
127 linux,code = <0x102>;
[all …]
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/axp/
H A Dboard_env_spec.h12 #define MV_6710_DEV_ID 0x6710
14 #define MV_6710_Z1_REV 0x0
19 #define MV_78130_DEV_ID 0x7813
20 #define MV_78160_DEV_ID 0x7816
21 #define MV_78230_DEV_ID 0x7823
22 #define MV_78260_DEV_ID 0x7826
23 #define MV_78460_DEV_ID 0x7846
24 #define MV_78000_DEV_ID 0x7888
26 #define MV_FPGA_DEV_ID 0x2107
28 #define MV_78XX0_Z1_REV 0x0
[all …]
/openbmc/qemu/include/hw/pci-host/
H A Dpnv_phb3_regs.h19 #define PBCQ_NEST_IRSN_COMPARE 0x1a
20 #define PBCQ_NEST_IRSN_COMP PPC_BITMASK(0, 18)
21 #define PBCQ_NEST_IRSN_MASK 0x1b
22 #define PBCQ_NEST_LSI_SRC_ID 0x1f
23 #define PBCQ_NEST_LSI_SRC PPC_BITMASK(0, 7)
24 #define PBCQ_NEST_REGS_COUNT 0x46
25 #define PBCQ_NEST_MMIO_BAR0 0x40
26 #define PBCQ_NEST_MMIO_BAR1 0x41
27 #define PBCQ_NEST_PHB_BAR 0x42
28 #define PBCQ_NEST_MMIO_MASK0 0x43
[all …]
/openbmc/linux/drivers/media/pci/cx18/
H A Dcx18-av-core.h32 CX18_AV_SVIDEO_LUMA1 = 0x10,
33 CX18_AV_SVIDEO_LUMA2 = 0x20,
34 CX18_AV_SVIDEO_LUMA3 = 0x30,
35 CX18_AV_SVIDEO_LUMA4 = 0x40,
36 CX18_AV_SVIDEO_LUMA5 = 0x50,
37 CX18_AV_SVIDEO_LUMA6 = 0x60,
38 CX18_AV_SVIDEO_LUMA7 = 0x70,
39 CX18_AV_SVIDEO_LUMA8 = 0x80,
40 CX18_AV_SVIDEO_CHROMA4 = 0x400,
41 CX18_AV_SVIDEO_CHROMA5 = 0x500,
[all …]
/openbmc/linux/drivers/clk/renesas/
H A Dr9a07g043-cpg.c60 {0, 1},
64 {0, 0},
68 {0, 1},
73 {0, 0},
88 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
135 0x514, 0),
137 0x518, 0),
139 0x518, 1),
143 0x518, 0),
145 0x518, 1),
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6sx-softing-vining-2000.dts22 reg = <0x80000000 0x40000000>;
29 pinctrl-0 = <&pinctrl_usb_otg1>;
49 pwms = <&pwm6 0 50000>;
55 pwms = <&pwm2 0 50000>;
61 pwms = <&pwm1 0 50000>;
95 pinctrl-0 = <&pinctrl_ecspi4>;
102 pinctrl-0 = <&pinctrl_enet1>;
112 #size-cells = <0>;
114 ethphy0: ethernet0-phy@0 {
115 reg = <0>;
[all …]
/openbmc/linux/drivers/mailbox/
H A Dapple-mailbox.c35 #define APPLE_ASC_MBOX_A2I_CONTROL 0x110
36 #define APPLE_ASC_MBOX_A2I_SEND0 0x800
37 #define APPLE_ASC_MBOX_A2I_SEND1 0x808
38 #define APPLE_ASC_MBOX_A2I_RECV0 0x810
39 #define APPLE_ASC_MBOX_A2I_RECV1 0x818
41 #define APPLE_ASC_MBOX_I2A_CONTROL 0x114
42 #define APPLE_ASC_MBOX_I2A_SEND0 0x820
43 #define APPLE_ASC_MBOX_I2A_SEND1 0x828
44 #define APPLE_ASC_MBOX_I2A_RECV0 0x830
45 #define APPLE_ASC_MBOX_I2A_RECV1 0x838
[all …]
/openbmc/linux/arch/mips/include/asm/
H A Dgt64120.h21 #define GT_CPU_OFS 0x000
23 #define GT_MULTI_OFS 0x120
26 #define GT_SCS10LD_OFS 0x008
27 #define GT_SCS10HD_OFS 0x010
28 #define GT_SCS32LD_OFS 0x018
29 #define GT_SCS32HD_OFS 0x020
30 #define GT_CS20LD_OFS 0x028
31 #define GT_CS20HD_OFS 0x030
32 #define GT_CS3BOOTLD_OFS 0x038
33 #define GT_CS3BOOTHD_OFS 0x040
[all …]
/openbmc/u-boot/include/
H A Dgt64120.h18 #define GT_CPU_OFS 0x000
20 #define GT_MULTI_OFS 0x120
23 #define GT_SCS10LD_OFS 0x008
24 #define GT_SCS10HD_OFS 0x010
25 #define GT_SCS32LD_OFS 0x018
26 #define GT_SCS32HD_OFS 0x020
27 #define GT_CS20LD_OFS 0x028
28 #define GT_CS20HD_OFS 0x030
29 #define GT_CS3BOOTLD_OFS 0x038
30 #define GT_CS3BOOTHD_OFS 0x040
[all …]
/openbmc/linux/drivers/mfd/
H A Drz-mtu3.c28 /******* MTU3 registers (original offset is +0x1200) *******/
30 [RZ_MTU3_CHAN_0] = MTU_8BIT_CH_0(0x104, 0x090, 0x100, 0x128, 0x101, 0x102, 0x103, 0x126),
31 [RZ_MTU3_CHAN_1] = MTU_8BIT_CH_1_2(0x184, 0x091, 0x185, 0x180, 0x194, 0x181, 0x182),
32 [RZ_MTU3_CHAN_2] = MTU_8BIT_CH_1_2(0x204, 0x092, 0x205, 0x200, 0x20c, 0x201, 0x202),
33 …[RZ_MTU3_CHAN_3] = MTU_8BIT_CH_3_4_6_7(0x008, 0x093, 0x02c, 0x000, 0x04c, 0x002, 0x004, 0x005, 0x0…
34 …[RZ_MTU3_CHAN_4] = MTU_8BIT_CH_3_4_6_7(0x009, 0x094, 0x02d, 0x001, 0x04d, 0x003, 0x006, 0x007, 0x0…
35 …[RZ_MTU3_CHAN_5] = MTU_8BIT_CH_5(0xab2, 0x1eb, 0xab4, 0xab6, 0xa84, 0xa85, 0xa86, 0xa94, 0xa95, 0x…
36 …[RZ_MTU3_CHAN_6] = MTU_8BIT_CH_3_4_6_7(0x808, 0x893, 0x82c, 0x800, 0x84c, 0x802, 0x804, 0x805, 0x8…
37 …[RZ_MTU3_CHAN_7] = MTU_8BIT_CH_3_4_6_7(0x809, 0x894, 0x82d, 0x801, 0x84d, 0x803, 0x806, 0x807, 0x8…
38 [RZ_MTU3_CHAN_8] = MTU_8BIT_CH_8(0x404, 0x098, 0x400, 0x406, 0x401, 0x402, 0x403)
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam437x-cm-t43.dts39 pinctrl-0 = <&cm_t43_led_pins>;
43 AM4372_IOPAD(0xa78, MUX_MODE7)
49 AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
50 AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
56 AM4372_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0 */
57 AM4372_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1 */
58 AM4372_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad10.mmc1_dat2 */
59 AM4372_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad11.mmc1_dat3 */
60 AM4372_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad12.mmc1_dat4 */
61 AM4372_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad13.mmc1_dat5 */
[all …]

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