141173abcSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2384740dcSRalf Baechle /* 3384740dcSRalf Baechle * Copyright (C) 2000, 2004, 2005 MIPS Technologies, Inc. 4384740dcSRalf Baechle * All rights reserved. 5384740dcSRalf Baechle * Authors: Carsten Langgaard <carstenl@mips.com> 6384740dcSRalf Baechle * Maciej W. Rozycki <macro@mips.com> 7384740dcSRalf Baechle * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) 8384740dcSRalf Baechle */ 9384740dcSRalf Baechle #ifndef _ASM_GT64120_H 10384740dcSRalf Baechle #define _ASM_GT64120_H 11384740dcSRalf Baechle 12384740dcSRalf Baechle #include <asm/addrspace.h> 13384740dcSRalf Baechle #include <asm/byteorder.h> 14384740dcSRalf Baechle 15384740dcSRalf Baechle #define MSK(n) ((1 << (n)) - 1) 16384740dcSRalf Baechle 17384740dcSRalf Baechle /* 18384740dcSRalf Baechle * Register offset addresses 19384740dcSRalf Baechle */ 20384740dcSRalf Baechle /* CPU Configuration. */ 21384740dcSRalf Baechle #define GT_CPU_OFS 0x000 22384740dcSRalf Baechle 23384740dcSRalf Baechle #define GT_MULTI_OFS 0x120 24384740dcSRalf Baechle 25384740dcSRalf Baechle /* CPU Address Decode. */ 26384740dcSRalf Baechle #define GT_SCS10LD_OFS 0x008 27384740dcSRalf Baechle #define GT_SCS10HD_OFS 0x010 28384740dcSRalf Baechle #define GT_SCS32LD_OFS 0x018 29384740dcSRalf Baechle #define GT_SCS32HD_OFS 0x020 30384740dcSRalf Baechle #define GT_CS20LD_OFS 0x028 31384740dcSRalf Baechle #define GT_CS20HD_OFS 0x030 32384740dcSRalf Baechle #define GT_CS3BOOTLD_OFS 0x038 33384740dcSRalf Baechle #define GT_CS3BOOTHD_OFS 0x040 34384740dcSRalf Baechle #define GT_PCI0IOLD_OFS 0x048 35384740dcSRalf Baechle #define GT_PCI0IOHD_OFS 0x050 36384740dcSRalf Baechle #define GT_PCI0M0LD_OFS 0x058 37384740dcSRalf Baechle #define GT_PCI0M0HD_OFS 0x060 38384740dcSRalf Baechle #define GT_ISD_OFS 0x068 39384740dcSRalf Baechle 40384740dcSRalf Baechle #define GT_PCI0M1LD_OFS 0x080 41384740dcSRalf Baechle #define GT_PCI0M1HD_OFS 0x088 42384740dcSRalf Baechle #define GT_PCI1IOLD_OFS 0x090 43384740dcSRalf Baechle #define GT_PCI1IOHD_OFS 0x098 44384740dcSRalf Baechle #define GT_PCI1M0LD_OFS 0x0a0 45384740dcSRalf Baechle #define GT_PCI1M0HD_OFS 0x0a8 46384740dcSRalf Baechle #define GT_PCI1M1LD_OFS 0x0b0 47384740dcSRalf Baechle #define GT_PCI1M1HD_OFS 0x0b8 48384740dcSRalf Baechle #define GT_PCI1M1LD_OFS 0x0b0 49384740dcSRalf Baechle #define GT_PCI1M1HD_OFS 0x0b8 50384740dcSRalf Baechle 51384740dcSRalf Baechle #define GT_SCS10AR_OFS 0x0d0 52384740dcSRalf Baechle #define GT_SCS32AR_OFS 0x0d8 53384740dcSRalf Baechle #define GT_CS20R_OFS 0x0e0 54384740dcSRalf Baechle #define GT_CS3BOOTR_OFS 0x0e8 55384740dcSRalf Baechle 56384740dcSRalf Baechle #define GT_PCI0IOREMAP_OFS 0x0f0 57384740dcSRalf Baechle #define GT_PCI0M0REMAP_OFS 0x0f8 58384740dcSRalf Baechle #define GT_PCI0M1REMAP_OFS 0x100 59384740dcSRalf Baechle #define GT_PCI1IOREMAP_OFS 0x108 60384740dcSRalf Baechle #define GT_PCI1M0REMAP_OFS 0x110 61384740dcSRalf Baechle #define GT_PCI1M1REMAP_OFS 0x118 62384740dcSRalf Baechle 63384740dcSRalf Baechle /* CPU Error Report. */ 64384740dcSRalf Baechle #define GT_CPUERR_ADDRLO_OFS 0x070 65384740dcSRalf Baechle #define GT_CPUERR_ADDRHI_OFS 0x078 66384740dcSRalf Baechle 67384740dcSRalf Baechle #define GT_CPUERR_DATALO_OFS 0x128 /* GT-64120A only */ 68384740dcSRalf Baechle #define GT_CPUERR_DATAHI_OFS 0x130 /* GT-64120A only */ 69384740dcSRalf Baechle #define GT_CPUERR_PARITY_OFS 0x138 /* GT-64120A only */ 70384740dcSRalf Baechle 71384740dcSRalf Baechle /* CPU Sync Barrier. */ 72384740dcSRalf Baechle #define GT_PCI0SYNC_OFS 0x0c0 73384740dcSRalf Baechle #define GT_PCI1SYNC_OFS 0x0c8 74384740dcSRalf Baechle 75384740dcSRalf Baechle /* SDRAM and Device Address Decode. */ 76384740dcSRalf Baechle #define GT_SCS0LD_OFS 0x400 77384740dcSRalf Baechle #define GT_SCS0HD_OFS 0x404 78384740dcSRalf Baechle #define GT_SCS1LD_OFS 0x408 79384740dcSRalf Baechle #define GT_SCS1HD_OFS 0x40c 80384740dcSRalf Baechle #define GT_SCS2LD_OFS 0x410 81384740dcSRalf Baechle #define GT_SCS2HD_OFS 0x414 82384740dcSRalf Baechle #define GT_SCS3LD_OFS 0x418 83384740dcSRalf Baechle #define GT_SCS3HD_OFS 0x41c 84384740dcSRalf Baechle #define GT_CS0LD_OFS 0x420 85384740dcSRalf Baechle #define GT_CS0HD_OFS 0x424 86384740dcSRalf Baechle #define GT_CS1LD_OFS 0x428 87384740dcSRalf Baechle #define GT_CS1HD_OFS 0x42c 88384740dcSRalf Baechle #define GT_CS2LD_OFS 0x430 89384740dcSRalf Baechle #define GT_CS2HD_OFS 0x434 90384740dcSRalf Baechle #define GT_CS3LD_OFS 0x438 91384740dcSRalf Baechle #define GT_CS3HD_OFS 0x43c 92384740dcSRalf Baechle #define GT_BOOTLD_OFS 0x440 93384740dcSRalf Baechle #define GT_BOOTHD_OFS 0x444 94384740dcSRalf Baechle 95384740dcSRalf Baechle #define GT_ADERR_OFS 0x470 96384740dcSRalf Baechle 97384740dcSRalf Baechle /* SDRAM Configuration. */ 98384740dcSRalf Baechle #define GT_SDRAM_CFG_OFS 0x448 99384740dcSRalf Baechle 100384740dcSRalf Baechle #define GT_SDRAM_OPMODE_OFS 0x474 101384740dcSRalf Baechle #define GT_SDRAM_BM_OFS 0x478 102384740dcSRalf Baechle #define GT_SDRAM_ADDRDECODE_OFS 0x47c 103384740dcSRalf Baechle 104384740dcSRalf Baechle /* SDRAM Parameters. */ 105384740dcSRalf Baechle #define GT_SDRAM_B0_OFS 0x44c 106384740dcSRalf Baechle #define GT_SDRAM_B1_OFS 0x450 107384740dcSRalf Baechle #define GT_SDRAM_B2_OFS 0x454 108384740dcSRalf Baechle #define GT_SDRAM_B3_OFS 0x458 109384740dcSRalf Baechle 110384740dcSRalf Baechle /* Device Parameters. */ 111384740dcSRalf Baechle #define GT_DEV_B0_OFS 0x45c 112384740dcSRalf Baechle #define GT_DEV_B1_OFS 0x460 113384740dcSRalf Baechle #define GT_DEV_B2_OFS 0x464 114384740dcSRalf Baechle #define GT_DEV_B3_OFS 0x468 115384740dcSRalf Baechle #define GT_DEV_BOOT_OFS 0x46c 116384740dcSRalf Baechle 117384740dcSRalf Baechle /* ECC. */ 118384740dcSRalf Baechle #define GT_ECC_ERRDATALO 0x480 /* GT-64120A only */ 119384740dcSRalf Baechle #define GT_ECC_ERRDATAHI 0x484 /* GT-64120A only */ 120384740dcSRalf Baechle #define GT_ECC_MEM 0x488 /* GT-64120A only */ 121384740dcSRalf Baechle #define GT_ECC_CALC 0x48c /* GT-64120A only */ 122384740dcSRalf Baechle #define GT_ECC_ERRADDR 0x490 /* GT-64120A only */ 123384740dcSRalf Baechle 124384740dcSRalf Baechle /* DMA Record. */ 125384740dcSRalf Baechle #define GT_DMA0_CNT_OFS 0x800 126384740dcSRalf Baechle #define GT_DMA1_CNT_OFS 0x804 127384740dcSRalf Baechle #define GT_DMA2_CNT_OFS 0x808 128384740dcSRalf Baechle #define GT_DMA3_CNT_OFS 0x80c 129384740dcSRalf Baechle #define GT_DMA0_SA_OFS 0x810 130384740dcSRalf Baechle #define GT_DMA1_SA_OFS 0x814 131384740dcSRalf Baechle #define GT_DMA2_SA_OFS 0x818 132384740dcSRalf Baechle #define GT_DMA3_SA_OFS 0x81c 133384740dcSRalf Baechle #define GT_DMA0_DA_OFS 0x820 134384740dcSRalf Baechle #define GT_DMA1_DA_OFS 0x824 135384740dcSRalf Baechle #define GT_DMA2_DA_OFS 0x828 136384740dcSRalf Baechle #define GT_DMA3_DA_OFS 0x82c 137384740dcSRalf Baechle #define GT_DMA0_NEXT_OFS 0x830 138384740dcSRalf Baechle #define GT_DMA1_NEXT_OFS 0x834 139384740dcSRalf Baechle #define GT_DMA2_NEXT_OFS 0x838 140384740dcSRalf Baechle #define GT_DMA3_NEXT_OFS 0x83c 141384740dcSRalf Baechle 142384740dcSRalf Baechle #define GT_DMA0_CUR_OFS 0x870 143384740dcSRalf Baechle #define GT_DMA1_CUR_OFS 0x874 144384740dcSRalf Baechle #define GT_DMA2_CUR_OFS 0x878 145384740dcSRalf Baechle #define GT_DMA3_CUR_OFS 0x87c 146384740dcSRalf Baechle 147384740dcSRalf Baechle /* DMA Channel Control. */ 148384740dcSRalf Baechle #define GT_DMA0_CTRL_OFS 0x840 149384740dcSRalf Baechle #define GT_DMA1_CTRL_OFS 0x844 150384740dcSRalf Baechle #define GT_DMA2_CTRL_OFS 0x848 151384740dcSRalf Baechle #define GT_DMA3_CTRL_OFS 0x84c 152384740dcSRalf Baechle 153384740dcSRalf Baechle /* DMA Arbiter. */ 154384740dcSRalf Baechle #define GT_DMA_ARB_OFS 0x860 155384740dcSRalf Baechle 156384740dcSRalf Baechle /* Timer/Counter. */ 157384740dcSRalf Baechle #define GT_TC0_OFS 0x850 158384740dcSRalf Baechle #define GT_TC1_OFS 0x854 159384740dcSRalf Baechle #define GT_TC2_OFS 0x858 160384740dcSRalf Baechle #define GT_TC3_OFS 0x85c 161384740dcSRalf Baechle 162384740dcSRalf Baechle #define GT_TC_CONTROL_OFS 0x864 163384740dcSRalf Baechle 164384740dcSRalf Baechle /* PCI Internal. */ 165384740dcSRalf Baechle #define GT_PCI0_CMD_OFS 0xc00 166384740dcSRalf Baechle #define GT_PCI0_TOR_OFS 0xc04 167384740dcSRalf Baechle #define GT_PCI0_BS_SCS10_OFS 0xc08 168384740dcSRalf Baechle #define GT_PCI0_BS_SCS32_OFS 0xc0c 169384740dcSRalf Baechle #define GT_PCI0_BS_CS20_OFS 0xc10 170384740dcSRalf Baechle #define GT_PCI0_BS_CS3BT_OFS 0xc14 171384740dcSRalf Baechle 172384740dcSRalf Baechle #define GT_PCI1_IACK_OFS 0xc30 173384740dcSRalf Baechle #define GT_PCI0_IACK_OFS 0xc34 174384740dcSRalf Baechle 175384740dcSRalf Baechle #define GT_PCI0_BARE_OFS 0xc3c 176384740dcSRalf Baechle #define GT_PCI0_PREFMBR_OFS 0xc40 177384740dcSRalf Baechle 178384740dcSRalf Baechle #define GT_PCI0_SCS10_BAR_OFS 0xc48 179384740dcSRalf Baechle #define GT_PCI0_SCS32_BAR_OFS 0xc4c 180384740dcSRalf Baechle #define GT_PCI0_CS20_BAR_OFS 0xc50 181384740dcSRalf Baechle #define GT_PCI0_CS3BT_BAR_OFS 0xc54 182384740dcSRalf Baechle #define GT_PCI0_SSCS10_BAR_OFS 0xc58 183384740dcSRalf Baechle #define GT_PCI0_SSCS32_BAR_OFS 0xc5c 184384740dcSRalf Baechle 185384740dcSRalf Baechle #define GT_PCI0_SCS3BT_BAR_OFS 0xc64 186384740dcSRalf Baechle 187384740dcSRalf Baechle #define GT_PCI1_CMD_OFS 0xc80 188384740dcSRalf Baechle #define GT_PCI1_TOR_OFS 0xc84 189384740dcSRalf Baechle #define GT_PCI1_BS_SCS10_OFS 0xc88 190384740dcSRalf Baechle #define GT_PCI1_BS_SCS32_OFS 0xc8c 191384740dcSRalf Baechle #define GT_PCI1_BS_CS20_OFS 0xc90 192384740dcSRalf Baechle #define GT_PCI1_BS_CS3BT_OFS 0xc94 193384740dcSRalf Baechle 194384740dcSRalf Baechle #define GT_PCI1_BARE_OFS 0xcbc 195384740dcSRalf Baechle #define GT_PCI1_PREFMBR_OFS 0xcc0 196384740dcSRalf Baechle 197384740dcSRalf Baechle #define GT_PCI1_SCS10_BAR_OFS 0xcc8 198384740dcSRalf Baechle #define GT_PCI1_SCS32_BAR_OFS 0xccc 199384740dcSRalf Baechle #define GT_PCI1_CS20_BAR_OFS 0xcd0 200384740dcSRalf Baechle #define GT_PCI1_CS3BT_BAR_OFS 0xcd4 201384740dcSRalf Baechle #define GT_PCI1_SSCS10_BAR_OFS 0xcd8 202384740dcSRalf Baechle #define GT_PCI1_SSCS32_BAR_OFS 0xcdc 203384740dcSRalf Baechle 204384740dcSRalf Baechle #define GT_PCI1_SCS3BT_BAR_OFS 0xce4 205384740dcSRalf Baechle 206384740dcSRalf Baechle #define GT_PCI1_CFGADDR_OFS 0xcf0 207384740dcSRalf Baechle #define GT_PCI1_CFGDATA_OFS 0xcf4 208384740dcSRalf Baechle #define GT_PCI0_CFGADDR_OFS 0xcf8 209384740dcSRalf Baechle #define GT_PCI0_CFGDATA_OFS 0xcfc 210384740dcSRalf Baechle 211384740dcSRalf Baechle /* Interrupts. */ 212384740dcSRalf Baechle #define GT_INTRCAUSE_OFS 0xc18 213384740dcSRalf Baechle #define GT_INTRMASK_OFS 0xc1c 214384740dcSRalf Baechle 215384740dcSRalf Baechle #define GT_PCI0_ICMASK_OFS 0xc24 216384740dcSRalf Baechle #define GT_PCI0_SERR0MASK_OFS 0xc28 217384740dcSRalf Baechle 218384740dcSRalf Baechle #define GT_CPU_INTSEL_OFS 0xc70 219384740dcSRalf Baechle #define GT_PCI0_INTSEL_OFS 0xc74 220384740dcSRalf Baechle 221384740dcSRalf Baechle #define GT_HINTRCAUSE_OFS 0xc98 222384740dcSRalf Baechle #define GT_HINTRMASK_OFS 0xc9c 223384740dcSRalf Baechle 224384740dcSRalf Baechle #define GT_PCI0_HICMASK_OFS 0xca4 225384740dcSRalf Baechle #define GT_PCI1_SERR1MASK_OFS 0xca8 226384740dcSRalf Baechle 227384740dcSRalf Baechle 228384740dcSRalf Baechle /* 229384740dcSRalf Baechle * I2O Support Registers 230384740dcSRalf Baechle */ 231384740dcSRalf Baechle #define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010 232384740dcSRalf Baechle #define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014 233384740dcSRalf Baechle #define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018 234384740dcSRalf Baechle #define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01c 235384740dcSRalf Baechle #define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020 236384740dcSRalf Baechle #define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024 237384740dcSRalf Baechle #define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028 238384740dcSRalf Baechle #define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02c 239384740dcSRalf Baechle #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030 240384740dcSRalf Baechle #define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034 241384740dcSRalf Baechle #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040 242384740dcSRalf Baechle #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044 243384740dcSRalf Baechle #define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050 244384740dcSRalf Baechle #define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054 245384740dcSRalf Baechle #define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060 246384740dcSRalf Baechle #define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064 247384740dcSRalf Baechle #define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068 248384740dcSRalf Baechle #define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06c 249384740dcSRalf Baechle #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070 250384740dcSRalf Baechle #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074 251384740dcSRalf Baechle #define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078 252384740dcSRalf Baechle #define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07c 253384740dcSRalf Baechle 254384740dcSRalf Baechle #define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c10 255384740dcSRalf Baechle #define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c14 256384740dcSRalf Baechle #define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c18 257384740dcSRalf Baechle #define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c1c 258384740dcSRalf Baechle #define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c20 259384740dcSRalf Baechle #define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c24 260384740dcSRalf Baechle #define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c28 261384740dcSRalf Baechle #define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c2c 262384740dcSRalf Baechle #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c30 263384740dcSRalf Baechle #define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c34 264384740dcSRalf Baechle #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c40 265384740dcSRalf Baechle #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c44 266384740dcSRalf Baechle #define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1c50 267384740dcSRalf Baechle #define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1c54 268384740dcSRalf Baechle #define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c60 269384740dcSRalf Baechle #define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c64 270384740dcSRalf Baechle #define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c68 271384740dcSRalf Baechle #define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c6c 272384740dcSRalf Baechle #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c70 273384740dcSRalf Baechle #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c74 274384740dcSRalf Baechle #define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c78 275384740dcSRalf Baechle #define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c7c 276384740dcSRalf Baechle 277384740dcSRalf Baechle /* 278384740dcSRalf Baechle * Register encodings 279384740dcSRalf Baechle */ 280384740dcSRalf Baechle #define GT_CPU_ENDIAN_SHF 12 281384740dcSRalf Baechle #define GT_CPU_ENDIAN_MSK (MSK(1) << GT_CPU_ENDIAN_SHF) 282384740dcSRalf Baechle #define GT_CPU_ENDIAN_BIT GT_CPU_ENDIAN_MSK 283384740dcSRalf Baechle #define GT_CPU_WR_SHF 16 284384740dcSRalf Baechle #define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF) 285384740dcSRalf Baechle #define GT_CPU_WR_BIT GT_CPU_WR_MSK 286384740dcSRalf Baechle #define GT_CPU_WR_DXDXDXDX 0 287384740dcSRalf Baechle #define GT_CPU_WR_DDDD 1 288384740dcSRalf Baechle 289384740dcSRalf Baechle 290384740dcSRalf Baechle #define GT_PCI_DCRM_SHF 21 291384740dcSRalf Baechle #define GT_PCI_LD_SHF 0 292384740dcSRalf Baechle #define GT_PCI_LD_MSK (MSK(15) << GT_PCI_LD_SHF) 293384740dcSRalf Baechle #define GT_PCI_HD_SHF 0 294384740dcSRalf Baechle #define GT_PCI_HD_MSK (MSK(7) << GT_PCI_HD_SHF) 295384740dcSRalf Baechle #define GT_PCI_REMAP_SHF 0 296384740dcSRalf Baechle #define GT_PCI_REMAP_MSK (MSK(11) << GT_PCI_REMAP_SHF) 297384740dcSRalf Baechle 298384740dcSRalf Baechle 299384740dcSRalf Baechle #define GT_CFGADDR_CFGEN_SHF 31 300384740dcSRalf Baechle #define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF) 301384740dcSRalf Baechle #define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK 302384740dcSRalf Baechle 303384740dcSRalf Baechle #define GT_CFGADDR_BUSNUM_SHF 16 304384740dcSRalf Baechle #define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF) 305384740dcSRalf Baechle 306384740dcSRalf Baechle #define GT_CFGADDR_DEVNUM_SHF 11 307384740dcSRalf Baechle #define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF) 308384740dcSRalf Baechle 309384740dcSRalf Baechle #define GT_CFGADDR_FUNCNUM_SHF 8 310384740dcSRalf Baechle #define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF) 311384740dcSRalf Baechle 312384740dcSRalf Baechle #define GT_CFGADDR_REGNUM_SHF 2 313384740dcSRalf Baechle #define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF) 314384740dcSRalf Baechle 315384740dcSRalf Baechle 316384740dcSRalf Baechle #define GT_SDRAM_BM_ORDER_SHF 2 317384740dcSRalf Baechle #define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF) 318384740dcSRalf Baechle #define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK 319384740dcSRalf Baechle #define GT_SDRAM_BM_ORDER_SUB 1 320384740dcSRalf Baechle #define GT_SDRAM_BM_ORDER_LIN 0 321384740dcSRalf Baechle 322384740dcSRalf Baechle #define GT_SDRAM_BM_RSVD_ALL1 0xffb 323384740dcSRalf Baechle 324384740dcSRalf Baechle 325384740dcSRalf Baechle #define GT_SDRAM_ADDRDECODE_ADDR_SHF 0 326384740dcSRalf Baechle #define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF) 327384740dcSRalf Baechle #define GT_SDRAM_ADDRDECODE_ADDR_0 0 328384740dcSRalf Baechle #define GT_SDRAM_ADDRDECODE_ADDR_1 1 329384740dcSRalf Baechle #define GT_SDRAM_ADDRDECODE_ADDR_2 2 330384740dcSRalf Baechle #define GT_SDRAM_ADDRDECODE_ADDR_3 3 331384740dcSRalf Baechle #define GT_SDRAM_ADDRDECODE_ADDR_4 4 332384740dcSRalf Baechle #define GT_SDRAM_ADDRDECODE_ADDR_5 5 333384740dcSRalf Baechle #define GT_SDRAM_ADDRDECODE_ADDR_6 6 334384740dcSRalf Baechle #define GT_SDRAM_ADDRDECODE_ADDR_7 7 335384740dcSRalf Baechle 336384740dcSRalf Baechle 337384740dcSRalf Baechle #define GT_SDRAM_B0_CASLAT_SHF 0 338384740dcSRalf Baechle #define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF) 339384740dcSRalf Baechle #define GT_SDRAM_B0_CASLAT_2 1 340384740dcSRalf Baechle #define GT_SDRAM_B0_CASLAT_3 2 341384740dcSRalf Baechle 342384740dcSRalf Baechle #define GT_SDRAM_B0_FTDIS_SHF 2 343384740dcSRalf Baechle #define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF) 344384740dcSRalf Baechle #define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK 345384740dcSRalf Baechle 346384740dcSRalf Baechle #define GT_SDRAM_B0_SRASPRCHG_SHF 3 347384740dcSRalf Baechle #define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF) 348384740dcSRalf Baechle #define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK 349384740dcSRalf Baechle #define GT_SDRAM_B0_SRASPRCHG_2 0 350384740dcSRalf Baechle #define GT_SDRAM_B0_SRASPRCHG_3 1 351384740dcSRalf Baechle 352384740dcSRalf Baechle #define GT_SDRAM_B0_B0COMPAB_SHF 4 353384740dcSRalf Baechle #define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF) 354384740dcSRalf Baechle #define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK 355384740dcSRalf Baechle 356384740dcSRalf Baechle #define GT_SDRAM_B0_64BITINT_SHF 5 357384740dcSRalf Baechle #define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF) 358384740dcSRalf Baechle #define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK 359384740dcSRalf Baechle #define GT_SDRAM_B0_64BITINT_2 0 360384740dcSRalf Baechle #define GT_SDRAM_B0_64BITINT_4 1 361384740dcSRalf Baechle 362384740dcSRalf Baechle #define GT_SDRAM_B0_BW_SHF 6 363384740dcSRalf Baechle #define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF) 364384740dcSRalf Baechle #define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK 365384740dcSRalf Baechle #define GT_SDRAM_B0_BW_32 0 366384740dcSRalf Baechle #define GT_SDRAM_B0_BW_64 1 367384740dcSRalf Baechle 368384740dcSRalf Baechle #define GT_SDRAM_B0_BLODD_SHF 7 369384740dcSRalf Baechle #define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF) 370384740dcSRalf Baechle #define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK 371384740dcSRalf Baechle 372384740dcSRalf Baechle #define GT_SDRAM_B0_PAR_SHF 8 373384740dcSRalf Baechle #define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF) 374384740dcSRalf Baechle #define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK 375384740dcSRalf Baechle 376384740dcSRalf Baechle #define GT_SDRAM_B0_BYPASS_SHF 9 377384740dcSRalf Baechle #define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF) 378384740dcSRalf Baechle #define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK 379384740dcSRalf Baechle 380384740dcSRalf Baechle #define GT_SDRAM_B0_SRAS2SCAS_SHF 10 381384740dcSRalf Baechle #define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF) 382384740dcSRalf Baechle #define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK 383384740dcSRalf Baechle #define GT_SDRAM_B0_SRAS2SCAS_2 0 384384740dcSRalf Baechle #define GT_SDRAM_B0_SRAS2SCAS_3 1 385384740dcSRalf Baechle 386384740dcSRalf Baechle #define GT_SDRAM_B0_SIZE_SHF 11 387384740dcSRalf Baechle #define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF) 388384740dcSRalf Baechle #define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK 389384740dcSRalf Baechle #define GT_SDRAM_B0_SIZE_16M 0 390384740dcSRalf Baechle #define GT_SDRAM_B0_SIZE_64M 1 391384740dcSRalf Baechle 392384740dcSRalf Baechle #define GT_SDRAM_B0_EXTPAR_SHF 12 393384740dcSRalf Baechle #define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF) 394384740dcSRalf Baechle #define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK 395384740dcSRalf Baechle 396384740dcSRalf Baechle #define GT_SDRAM_B0_BLEN_SHF 13 397384740dcSRalf Baechle #define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF) 398384740dcSRalf Baechle #define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK 399384740dcSRalf Baechle #define GT_SDRAM_B0_BLEN_8 0 400384740dcSRalf Baechle #define GT_SDRAM_B0_BLEN_4 1 401384740dcSRalf Baechle 402384740dcSRalf Baechle 403384740dcSRalf Baechle #define GT_SDRAM_CFG_REFINT_SHF 0 404384740dcSRalf Baechle #define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF) 405384740dcSRalf Baechle 406384740dcSRalf Baechle #define GT_SDRAM_CFG_NINTERLEAVE_SHF 14 407384740dcSRalf Baechle #define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF) 408384740dcSRalf Baechle #define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK 409384740dcSRalf Baechle 410384740dcSRalf Baechle #define GT_SDRAM_CFG_RMW_SHF 15 411384740dcSRalf Baechle #define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF) 412384740dcSRalf Baechle #define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK 413384740dcSRalf Baechle 414384740dcSRalf Baechle #define GT_SDRAM_CFG_NONSTAGREF_SHF 16 415384740dcSRalf Baechle #define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF) 416384740dcSRalf Baechle #define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK 417384740dcSRalf Baechle 418384740dcSRalf Baechle #define GT_SDRAM_CFG_DUPCNTL_SHF 19 419384740dcSRalf Baechle #define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF) 420384740dcSRalf Baechle #define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK 421384740dcSRalf Baechle 422384740dcSRalf Baechle #define GT_SDRAM_CFG_DUPBA_SHF 20 423384740dcSRalf Baechle #define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF) 424384740dcSRalf Baechle #define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK 425384740dcSRalf Baechle 426384740dcSRalf Baechle #define GT_SDRAM_CFG_DUPEOT0_SHF 21 427384740dcSRalf Baechle #define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF) 428384740dcSRalf Baechle #define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK 429384740dcSRalf Baechle 430384740dcSRalf Baechle #define GT_SDRAM_CFG_DUPEOT1_SHF 22 431384740dcSRalf Baechle #define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF) 432384740dcSRalf Baechle #define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK 433384740dcSRalf Baechle 434384740dcSRalf Baechle #define GT_SDRAM_OPMODE_OP_SHF 0 435384740dcSRalf Baechle #define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF) 436384740dcSRalf Baechle #define GT_SDRAM_OPMODE_OP_NORMAL 0 437384740dcSRalf Baechle #define GT_SDRAM_OPMODE_OP_NOP 1 438384740dcSRalf Baechle #define GT_SDRAM_OPMODE_OP_PRCHG 2 439384740dcSRalf Baechle #define GT_SDRAM_OPMODE_OP_MODE 3 440384740dcSRalf Baechle #define GT_SDRAM_OPMODE_OP_CBR 4 441384740dcSRalf Baechle 442384740dcSRalf Baechle #define GT_TC_CONTROL_ENTC0_SHF 0 443384740dcSRalf Baechle #define GT_TC_CONTROL_ENTC0_MSK (MSK(1) << GT_TC_CONTROL_ENTC0_SHF) 444384740dcSRalf Baechle #define GT_TC_CONTROL_ENTC0_BIT GT_TC_CONTROL_ENTC0_MSK 445384740dcSRalf Baechle #define GT_TC_CONTROL_SELTC0_SHF 1 446384740dcSRalf Baechle #define GT_TC_CONTROL_SELTC0_MSK (MSK(1) << GT_TC_CONTROL_SELTC0_SHF) 447384740dcSRalf Baechle #define GT_TC_CONTROL_SELTC0_BIT GT_TC_CONTROL_SELTC0_MSK 448384740dcSRalf Baechle 449384740dcSRalf Baechle 450384740dcSRalf Baechle #define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0 451384740dcSRalf Baechle #define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF) 452384740dcSRalf Baechle #define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK 453384740dcSRalf Baechle 454384740dcSRalf Baechle #define GT_PCI0_BARE_SWSCS32DIS_SHF 1 455384740dcSRalf Baechle #define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF) 456384740dcSRalf Baechle #define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK 457384740dcSRalf Baechle 458384740dcSRalf Baechle #define GT_PCI0_BARE_SWSCS10DIS_SHF 2 459384740dcSRalf Baechle #define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF) 460384740dcSRalf Baechle #define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK 461384740dcSRalf Baechle 462384740dcSRalf Baechle #define GT_PCI0_BARE_INTIODIS_SHF 3 463384740dcSRalf Baechle #define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF) 464384740dcSRalf Baechle #define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK 465384740dcSRalf Baechle 466384740dcSRalf Baechle #define GT_PCI0_BARE_INTMEMDIS_SHF 4 467384740dcSRalf Baechle #define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF) 468384740dcSRalf Baechle #define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK 469384740dcSRalf Baechle 470384740dcSRalf Baechle #define GT_PCI0_BARE_CS3BOOTDIS_SHF 5 471384740dcSRalf Baechle #define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF) 472384740dcSRalf Baechle #define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK 473384740dcSRalf Baechle 474384740dcSRalf Baechle #define GT_PCI0_BARE_CS20DIS_SHF 6 475384740dcSRalf Baechle #define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF) 476384740dcSRalf Baechle #define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK 477384740dcSRalf Baechle 478384740dcSRalf Baechle #define GT_PCI0_BARE_SCS32DIS_SHF 7 479384740dcSRalf Baechle #define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF) 480384740dcSRalf Baechle #define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK 481384740dcSRalf Baechle 482384740dcSRalf Baechle #define GT_PCI0_BARE_SCS10DIS_SHF 8 483384740dcSRalf Baechle #define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF) 484384740dcSRalf Baechle #define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK 485384740dcSRalf Baechle 486384740dcSRalf Baechle 487384740dcSRalf Baechle #define GT_INTRCAUSE_MASABORT0_SHF 18 488384740dcSRalf Baechle #define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF) 489384740dcSRalf Baechle #define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK 490384740dcSRalf Baechle 491384740dcSRalf Baechle #define GT_INTRCAUSE_TARABORT0_SHF 19 492384740dcSRalf Baechle #define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF) 493384740dcSRalf Baechle #define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK 494384740dcSRalf Baechle 495384740dcSRalf Baechle 496384740dcSRalf Baechle #define GT_PCI0_CFGADDR_REGNUM_SHF 2 497384740dcSRalf Baechle #define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF) 498384740dcSRalf Baechle #define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8 499384740dcSRalf Baechle #define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF) 500384740dcSRalf Baechle #define GT_PCI0_CFGADDR_DEVNUM_SHF 11 501384740dcSRalf Baechle #define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF) 502384740dcSRalf Baechle #define GT_PCI0_CFGADDR_BUSNUM_SHF 16 503384740dcSRalf Baechle #define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF) 504384740dcSRalf Baechle #define GT_PCI0_CFGADDR_CONFIGEN_SHF 31 505384740dcSRalf Baechle #define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF) 506384740dcSRalf Baechle #define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK 507384740dcSRalf Baechle 508384740dcSRalf Baechle #define GT_PCI0_CMD_MBYTESWAP_SHF 0 509384740dcSRalf Baechle #define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF) 510384740dcSRalf Baechle #define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK 511384740dcSRalf Baechle #define GT_PCI0_CMD_MWORDSWAP_SHF 10 512384740dcSRalf Baechle #define GT_PCI0_CMD_MWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF) 513384740dcSRalf Baechle #define GT_PCI0_CMD_MWORDSWAP_BIT GT_PCI0_CMD_MWORDSWAP_MSK 514384740dcSRalf Baechle #define GT_PCI0_CMD_SBYTESWAP_SHF 16 515384740dcSRalf Baechle #define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF) 516384740dcSRalf Baechle #define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK 517384740dcSRalf Baechle #define GT_PCI0_CMD_SWORDSWAP_SHF 11 518384740dcSRalf Baechle #define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF) 519384740dcSRalf Baechle #define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK 520384740dcSRalf Baechle 521384740dcSRalf Baechle #define GT_INTR_T0EXP_SHF 8 522384740dcSRalf Baechle #define GT_INTR_T0EXP_MSK (MSK(1) << GT_INTR_T0EXP_SHF) 523384740dcSRalf Baechle #define GT_INTR_T0EXP_BIT GT_INTR_T0EXP_MSK 524384740dcSRalf Baechle #define GT_INTR_RETRYCTR0_SHF 20 525384740dcSRalf Baechle #define GT_INTR_RETRYCTR0_MSK (MSK(1) << GT_INTR_RETRYCTR0_SHF) 526384740dcSRalf Baechle #define GT_INTR_RETRYCTR0_BIT GT_INTR_RETRYCTR0_MSK 527384740dcSRalf Baechle 528384740dcSRalf Baechle /* 529384740dcSRalf Baechle * Misc 530384740dcSRalf Baechle */ 531384740dcSRalf Baechle #define GT_DEF_PCI0_IO_BASE 0x10000000UL 532384740dcSRalf Baechle #define GT_DEF_PCI0_IO_SIZE 0x02000000UL 533384740dcSRalf Baechle #define GT_DEF_PCI0_MEM0_BASE 0x12000000UL 534384740dcSRalf Baechle #define GT_DEF_PCI0_MEM0_SIZE 0x02000000UL 535384740dcSRalf Baechle #define GT_DEF_BASE 0x14000000UL 536384740dcSRalf Baechle 537384740dcSRalf Baechle #define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */ 538384740dcSRalf Baechle #define GT_LATTIM_MIN 6 /* Minimum lat */ 539384740dcSRalf Baechle 540384740dcSRalf Baechle /* 541384740dcSRalf Baechle * The gt64120_dep.h file must define the following macros 542384740dcSRalf Baechle * 543384740dcSRalf Baechle * GT_READ(ofs, data_pointer) 544384740dcSRalf Baechle * GT_WRITE(ofs, data) - read/write GT64120 registers in 32bit 545384740dcSRalf Baechle * 546384740dcSRalf Baechle * TIMER - gt64120 timer irq, temporary solution until 547384740dcSRalf Baechle * full gt64120 cascade interrupt support is in place 548384740dcSRalf Baechle */ 549384740dcSRalf Baechle 550384740dcSRalf Baechle #include <mach-gt64120.h> 551384740dcSRalf Baechle 552384740dcSRalf Baechle /* 553384740dcSRalf Baechle * Because of an error/peculiarity in the Galileo chip, we need to swap the 554384740dcSRalf Baechle * bytes when running bigendian. We also provide non-swapping versions. 555384740dcSRalf Baechle */ 556384740dcSRalf Baechle #define __GT_READ(ofs) \ 557384740dcSRalf Baechle (*(volatile u32 *)(GT64120_BASE+(ofs))) 558384740dcSRalf Baechle #define __GT_WRITE(ofs, data) \ 559384740dcSRalf Baechle do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0) 560384740dcSRalf Baechle #define GT_READ(ofs) le32_to_cpu(__GT_READ(ofs)) 561384740dcSRalf Baechle #define GT_WRITE(ofs, data) __GT_WRITE(ofs, cpu_to_le32(data)) 562384740dcSRalf Baechle 563384740dcSRalf Baechle extern void gt641xx_set_base_clock(unsigned int clock); 564384740dcSRalf Baechle extern int gt641xx_timer0_state(void); 565384740dcSRalf Baechle 566384740dcSRalf Baechle #endif /* _ASM_GT64120_H */ 567