Lines Matching +full:0 +full:x838
60 {0, 1},
64 {0, 0},
68 {0, 1},
73 {0, 0},
88 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
135 0x514, 0),
137 0x518, 0),
139 0x518, 1),
143 0x518, 0),
145 0x518, 1),
148 0x52c, 0),
150 0x52c, 1),
152 0x534, 0),
154 0x534, 1),
156 0x534, 2),
158 0x538, 0),
160 0x548, 0),
162 0x548, 1),
164 0x550, 0),
166 0x550, 1),
168 0x554, 0),
170 0x554, 1),
172 0x554, 2),
174 0x554, 3),
176 0x554, 4),
178 0x554, 5),
180 0x554, 6),
182 0x554, 7),
184 0x570, 0),
186 0x570, 1),
188 0x570, 2),
190 0x570, 3),
192 0x570, 4),
194 0x570, 5),
196 0x570, 6),
198 0x570, 7),
200 0x578, 0),
202 0x578, 1),
204 0x578, 2),
206 0x578, 3),
208 0x57c, 0),
210 0x57c, 0),
212 0x57c, 1),
214 0x57c, 1),
216 0x580, 0),
218 0x580, 1),
220 0x580, 2),
222 0x580, 3),
224 0x584, 0),
226 0x584, 1),
228 0x584, 2),
230 0x584, 3),
232 0x584, 4),
234 0x588, 0),
236 0x588, 1),
238 0x590, 0),
240 0x590, 1),
242 0x590, 2),
244 0x594, 0),
246 0x598, 0),
248 0x5a8, 0),
250 0x5a8, 1),
252 0x5ac, 0),
255 0x608, 0),
261 DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0),
262 DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1),
263 DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0),
266 DEF_RST(R9A07G043_IAX45_RESETN, 0x818, 0),
268 DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0),
269 DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1),
270 DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0),
271 DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1),
272 DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2),
273 DEF_RST(R9A07G043_MTU_X_PRESET_MTU3, 0x838, 0),
274 DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0),
275 DEF_RST(R9A07G043_SPI_RST, 0x850, 0),
276 DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),
277 DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1),
278 DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0),
279 DEF_RST(R9A07G043_SSI1_RST_M2_REG, 0x870, 1),
280 DEF_RST(R9A07G043_SSI2_RST_M2_REG, 0x870, 2),
281 DEF_RST(R9A07G043_SSI3_RST_M2_REG, 0x870, 3),
282 DEF_RST(R9A07G043_USB_U2H0_HRESETN, 0x878, 0),
283 DEF_RST(R9A07G043_USB_U2H1_HRESETN, 0x878, 1),
284 DEF_RST(R9A07G043_USB_U2P_EXL_SYSRST, 0x878, 2),
285 DEF_RST(R9A07G043_USB_PRESETN, 0x878, 3),
286 DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0),
287 DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1),
288 DEF_RST(R9A07G043_I2C0_MRST, 0x880, 0),
289 DEF_RST(R9A07G043_I2C1_MRST, 0x880, 1),
290 DEF_RST(R9A07G043_I2C2_MRST, 0x880, 2),
291 DEF_RST(R9A07G043_I2C3_MRST, 0x880, 3),
292 DEF_RST(R9A07G043_SCIF0_RST_SYSTEM_N, 0x884, 0),
293 DEF_RST(R9A07G043_SCIF1_RST_SYSTEM_N, 0x884, 1),
294 DEF_RST(R9A07G043_SCIF2_RST_SYSTEM_N, 0x884, 2),
295 DEF_RST(R9A07G043_SCIF3_RST_SYSTEM_N, 0x884, 3),
296 DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4),
297 DEF_RST(R9A07G043_SCI0_RST, 0x888, 0),
298 DEF_RST(R9A07G043_SCI1_RST, 0x888, 1),
299 DEF_RST(R9A07G043_RSPI0_RST, 0x890, 0),
300 DEF_RST(R9A07G043_RSPI1_RST, 0x890, 1),
301 DEF_RST(R9A07G043_RSPI2_RST, 0x890, 2),
302 DEF_RST(R9A07G043_CANFD_RSTP_N, 0x894, 0),
303 DEF_RST(R9A07G043_CANFD_RSTC_N, 0x894, 1),
304 DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0),
305 DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1),
306 DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2),
307 DEF_RST(R9A07G043_ADC_PRESETN, 0x8a8, 0),
308 DEF_RST(R9A07G043_ADC_ADRST_N, 0x8a8, 1),
309 DEF_RST(R9A07G043_TSU_PRESETN, 0x8ac, 0),
311 DEF_RST(R9A07G043_NCEPLIC_ARESETN, 0x908, 0),