1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 28fc8598eSJerry Chuang #ifndef _R819XU_PHYREG_H 38fc8598eSJerry Chuang #define _R819XU_PHYREG_H 48fc8598eSJerry Chuang 52160e944SSanjeev Sharma #define RF_DATA 0x1d4 /* FW will write RF data in the register.*/ 68fc8598eSJerry Chuang 72160e944SSanjeev Sharma /* page8 */ 82160e944SSanjeev Sharma #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ 98fc8598eSJerry Chuang #define rFPGA0_TxGainStage 0x80c 108fc8598eSJerry Chuang #define rFPGA0_XA_HSSIParameter1 0x820 118fc8598eSJerry Chuang #define rFPGA0_XA_HSSIParameter2 0x824 128fc8598eSJerry Chuang #define rFPGA0_XB_HSSIParameter1 0x828 138fc8598eSJerry Chuang #define rFPGA0_XB_HSSIParameter2 0x82c 148fc8598eSJerry Chuang #define rFPGA0_XC_HSSIParameter1 0x830 158fc8598eSJerry Chuang #define rFPGA0_XC_HSSIParameter2 0x834 168fc8598eSJerry Chuang #define rFPGA0_XD_HSSIParameter1 0x838 178fc8598eSJerry Chuang #define rFPGA0_XD_HSSIParameter2 0x83c 188fc8598eSJerry Chuang #define rFPGA0_XA_LSSIParameter 0x840 198fc8598eSJerry Chuang #define rFPGA0_XB_LSSIParameter 0x844 208fc8598eSJerry Chuang #define rFPGA0_XC_LSSIParameter 0x848 218fc8598eSJerry Chuang #define rFPGA0_XD_LSSIParameter 0x84c 228fc8598eSJerry Chuang #define rFPGA0_XAB_SwitchControl 0x858 238fc8598eSJerry Chuang #define rFPGA0_XCD_SwitchControl 0x85c 248fc8598eSJerry Chuang #define rFPGA0_XA_RFInterfaceOE 0x860 258fc8598eSJerry Chuang #define rFPGA0_XB_RFInterfaceOE 0x864 268fc8598eSJerry Chuang #define rFPGA0_XC_RFInterfaceOE 0x868 278fc8598eSJerry Chuang #define rFPGA0_XD_RFInterfaceOE 0x86c 288fc8598eSJerry Chuang #define rFPGA0_XAB_RFInterfaceSW 0x870 298fc8598eSJerry Chuang #define rFPGA0_XCD_RFInterfaceSW 0x874 308fc8598eSJerry Chuang #define rFPGA0_XAB_RFParameter 0x878 318fc8598eSJerry Chuang #define rFPGA0_XCD_RFParameter 0x87c 328fc8598eSJerry Chuang #define rFPGA0_AnalogParameter1 0x880 338fc8598eSJerry Chuang #define rFPGA0_AnalogParameter4 0x88c 348fc8598eSJerry Chuang #define rFPGA0_XA_LSSIReadBack 0x8a0 358fc8598eSJerry Chuang #define rFPGA0_XB_LSSIReadBack 0x8a4 368fc8598eSJerry Chuang #define rFPGA0_XC_LSSIReadBack 0x8a8 378fc8598eSJerry Chuang #define rFPGA0_XD_LSSIReadBack 0x8ac 388fc8598eSJerry Chuang #define rFPGA0_XAB_RFInterfaceRB 0x8e0 398fc8598eSJerry Chuang #define rFPGA0_XCD_RFInterfaceRB 0x8e4 408fc8598eSJerry Chuang 412160e944SSanjeev Sharma /* page 9 */ 422160e944SSanjeev Sharma #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ 438fc8598eSJerry Chuang 442160e944SSanjeev Sharma /* page a */ 458fc8598eSJerry Chuang #define rCCK0_System 0xa00 468fc8598eSJerry Chuang #define rCCK0_AFESetting 0xa04 478fc8598eSJerry Chuang #define rCCK0_CCA 0xa08 488fc8598eSJerry Chuang #define rCCK0_TxFilter1 0xa20 498fc8598eSJerry Chuang #define rCCK0_TxFilter2 0xa24 502160e944SSanjeev Sharma #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 518fc8598eSJerry Chuang 522160e944SSanjeev Sharma /* page c */ 538fc8598eSJerry Chuang #define rOFDM0_TRxPathEnable 0xc04 542160e944SSanjeev Sharma #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 55086a76b9SKimberly Brown #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imbalance matrix */ 568fc8598eSJerry Chuang #define rOFDM0_XBRxAFE 0xc18 578fc8598eSJerry Chuang #define rOFDM0_XBRxIQImbalance 0xc1c 588fc8598eSJerry Chuang #define rOFDM0_XCRxAFE 0xc20 598fc8598eSJerry Chuang #define rOFDM0_XCRxIQImbalance 0xc24 608fc8598eSJerry Chuang #define rOFDM0_XDRxAFE 0xc28 618fc8598eSJerry Chuang #define rOFDM0_XDRxIQImbalance 0xc2c 622160e944SSanjeev Sharma #define rOFDM0_RxDetector1 0xc30 /* PD,BW & SBD */ 632160e944SSanjeev Sharma #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync.*/ 642160e944SSanjeev Sharma #define rOFDM0_RxDetector3 0xc38 /* Frame Sync.*/ 652160e944SSanjeev Sharma #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 668fc8598eSJerry Chuang #define rOFDM0_XAAGCCore1 0xc50 678fc8598eSJerry Chuang #define rOFDM0_XAAGCCore2 0xc54 688fc8598eSJerry Chuang #define rOFDM0_XBAGCCore1 0xc58 698fc8598eSJerry Chuang #define rOFDM0_XBAGCCore2 0xc5c 708fc8598eSJerry Chuang #define rOFDM0_XCAGCCore1 0xc60 718fc8598eSJerry Chuang #define rOFDM0_XCAGCCore2 0xc64 728fc8598eSJerry Chuang #define rOFDM0_XDAGCCore1 0xc68 738fc8598eSJerry Chuang #define rOFDM0_XDAGCCore2 0xc6c 748fc8598eSJerry Chuang #define rOFDM0_XATxIQImbalance 0xc80 758fc8598eSJerry Chuang #define rOFDM0_XATxAFE 0xc84 768fc8598eSJerry Chuang #define rOFDM0_XBTxIQImbalance 0xc88 778fc8598eSJerry Chuang #define rOFDM0_XBTxAFE 0xc8c 788fc8598eSJerry Chuang #define rOFDM0_XCTxIQImbalance 0xc90 798fc8598eSJerry Chuang #define rOFDM0_XCTxAFE 0xc94 808fc8598eSJerry Chuang #define rOFDM0_XDTxIQImbalance 0xc98 818fc8598eSJerry Chuang #define rOFDM0_XDTxAFE 0xc9c 828fc8598eSJerry Chuang 832160e944SSanjeev Sharma /* page d */ 848fc8598eSJerry Chuang #define rOFDM1_LSTF 0xd00 858fc8598eSJerry Chuang #define rOFDM1_TRxPathEnable 0xd04 868fc8598eSJerry Chuang 872160e944SSanjeev Sharma /* page e */ 888fc8598eSJerry Chuang #define rTxAGC_Rate18_06 0xe00 898fc8598eSJerry Chuang #define rTxAGC_Rate54_24 0xe04 908fc8598eSJerry Chuang #define rTxAGC_CCK_Mcs32 0xe08 918fc8598eSJerry Chuang #define rTxAGC_Mcs03_Mcs00 0xe10 928fc8598eSJerry Chuang #define rTxAGC_Mcs07_Mcs04 0xe14 938fc8598eSJerry Chuang #define rTxAGC_Mcs11_Mcs08 0xe18 948fc8598eSJerry Chuang #define rTxAGC_Mcs15_Mcs12 0xe1c 958fc8598eSJerry Chuang 962160e944SSanjeev Sharma /* RF 972160e944SSanjeev Sharma * Zebra1 982160e944SSanjeev Sharma */ 998fc8598eSJerry Chuang #define rZebra1_Channel 0x7 1008fc8598eSJerry Chuang 1012160e944SSanjeev Sharma /* Zebra4 */ 1028fc8598eSJerry Chuang #define rGlobalCtrl 0 1038fc8598eSJerry Chuang 1042160e944SSanjeev Sharma /* Bit Mask 105531db655SJohn Whitmore * page-8 1062160e944SSanjeev Sharma */ 1078fc8598eSJerry Chuang #define bRFMOD 0x1 1088fc8598eSJerry Chuang #define bCCKEn 0x1000000 1098fc8598eSJerry Chuang #define bOFDMEn 0x2000000 1108fc8598eSJerry Chuang #define bXBTxAGC 0xf00 1118fc8598eSJerry Chuang #define bXCTxAGC 0xf000 1128fc8598eSJerry Chuang #define b3WireDataLength 0x800 1138fc8598eSJerry Chuang #define b3WireAddressLength 0x400 1148fc8598eSJerry Chuang #define bRFSI_RFENV 0x10 1152160e944SSanjeev Sharma #define bLSSIReadAddress 0x3f000000 /* LSSI "Read" Address */ 1162160e944SSanjeev Sharma #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ 1178fc8598eSJerry Chuang #define bLSSIReadBackData 0xfff 1188fc8598eSJerry Chuang #define bXtalCap 0x0f000000 1198fc8598eSJerry Chuang 1202160e944SSanjeev Sharma /* page-a */ 1218fc8598eSJerry Chuang #define bCCKSideBand 0x10 1228fc8598eSJerry Chuang 1232160e944SSanjeev Sharma /* page e */ 1248fc8598eSJerry Chuang #define bTxAGCRateCCK 0x7f00 1258fc8598eSJerry Chuang 1262160e944SSanjeev Sharma /* RF 1272160e944SSanjeev Sharma * Zebra1 1282160e944SSanjeev Sharma */ 1298fc8598eSJerry Chuang #define bZebra1_ChannelNum 0xf80 1308fc8598eSJerry Chuang 1312160e944SSanjeev Sharma /* RTL8258 */ 1322160e944SSanjeev Sharma /* for PutRegsetting & GetRegSetting BitMask */ 1338fc8598eSJerry Chuang #define bMaskByte0 0xff 1348fc8598eSJerry Chuang #define bMaskByte1 0xff00 1358fc8598eSJerry Chuang #define bMaskByte2 0xff0000 1368fc8598eSJerry Chuang #define bMaskHWord 0xffff0000 1378fc8598eSJerry Chuang #define bMaskLWord 0x0000ffff 1388fc8598eSJerry Chuang #define bMaskDWord 0xffffffff 1398fc8598eSJerry Chuang 1402160e944SSanjeev Sharma /* for PutRFRegsetting & GetRFRegSetting BitMask */ 1418fc8598eSJerry Chuang #define bMask12Bits 0xfff 1428fc8598eSJerry Chuang 1432160e944SSanjeev Sharma #endif /* __INC_HAL8190PCIPHYREG_H */ 144