Lines Matching +full:0 +full:x838

18 #define GT_CPU_OFS		0x000
20 #define GT_MULTI_OFS 0x120
23 #define GT_SCS10LD_OFS 0x008
24 #define GT_SCS10HD_OFS 0x010
25 #define GT_SCS32LD_OFS 0x018
26 #define GT_SCS32HD_OFS 0x020
27 #define GT_CS20LD_OFS 0x028
28 #define GT_CS20HD_OFS 0x030
29 #define GT_CS3BOOTLD_OFS 0x038
30 #define GT_CS3BOOTHD_OFS 0x040
31 #define GT_PCI0IOLD_OFS 0x048
32 #define GT_PCI0IOHD_OFS 0x050
33 #define GT_PCI0M0LD_OFS 0x058
34 #define GT_PCI0M0HD_OFS 0x060
35 #define GT_ISD_OFS 0x068
37 #define GT_PCI0M1LD_OFS 0x080
38 #define GT_PCI0M1HD_OFS 0x088
39 #define GT_PCI1IOLD_OFS 0x090
40 #define GT_PCI1IOHD_OFS 0x098
41 #define GT_PCI1M0LD_OFS 0x0a0
42 #define GT_PCI1M0HD_OFS 0x0a8
43 #define GT_PCI1M1LD_OFS 0x0b0
44 #define GT_PCI1M1HD_OFS 0x0b8
45 #define GT_PCI1M1LD_OFS 0x0b0
46 #define GT_PCI1M1HD_OFS 0x0b8
48 #define GT_SCS10AR_OFS 0x0d0
49 #define GT_SCS32AR_OFS 0x0d8
50 #define GT_CS20R_OFS 0x0e0
51 #define GT_CS3BOOTR_OFS 0x0e8
53 #define GT_PCI0IOREMAP_OFS 0x0f0
54 #define GT_PCI0M0REMAP_OFS 0x0f8
55 #define GT_PCI0M1REMAP_OFS 0x100
56 #define GT_PCI1IOREMAP_OFS 0x108
57 #define GT_PCI1M0REMAP_OFS 0x110
58 #define GT_PCI1M1REMAP_OFS 0x118
61 #define GT_CPUERR_ADDRLO_OFS 0x070
62 #define GT_CPUERR_ADDRHI_OFS 0x078
64 #define GT_CPUERR_DATALO_OFS 0x128 /* GT-64120A only */
65 #define GT_CPUERR_DATAHI_OFS 0x130 /* GT-64120A only */
66 #define GT_CPUERR_PARITY_OFS 0x138 /* GT-64120A only */
69 #define GT_PCI0SYNC_OFS 0x0c0
70 #define GT_PCI1SYNC_OFS 0x0c8
73 #define GT_SCS0LD_OFS 0x400
74 #define GT_SCS0HD_OFS 0x404
75 #define GT_SCS1LD_OFS 0x408
76 #define GT_SCS1HD_OFS 0x40c
77 #define GT_SCS2LD_OFS 0x410
78 #define GT_SCS2HD_OFS 0x414
79 #define GT_SCS3LD_OFS 0x418
80 #define GT_SCS3HD_OFS 0x41c
81 #define GT_CS0LD_OFS 0x420
82 #define GT_CS0HD_OFS 0x424
83 #define GT_CS1LD_OFS 0x428
84 #define GT_CS1HD_OFS 0x42c
85 #define GT_CS2LD_OFS 0x430
86 #define GT_CS2HD_OFS 0x434
87 #define GT_CS3LD_OFS 0x438
88 #define GT_CS3HD_OFS 0x43c
89 #define GT_BOOTLD_OFS 0x440
90 #define GT_BOOTHD_OFS 0x444
92 #define GT_ADERR_OFS 0x470
95 #define GT_SDRAM_CFG_OFS 0x448
97 #define GT_SDRAM_OPMODE_OFS 0x474
98 #define GT_SDRAM_BM_OFS 0x478
99 #define GT_SDRAM_ADDRDECODE_OFS 0x47c
102 #define GT_SDRAM_B0_OFS 0x44c
103 #define GT_SDRAM_B1_OFS 0x450
104 #define GT_SDRAM_B2_OFS 0x454
105 #define GT_SDRAM_B3_OFS 0x458
108 #define GT_DEV_B0_OFS 0x45c
109 #define GT_DEV_B1_OFS 0x460
110 #define GT_DEV_B2_OFS 0x464
111 #define GT_DEV_B3_OFS 0x468
112 #define GT_DEV_BOOT_OFS 0x46c
115 #define GT_ECC_ERRDATALO 0x480 /* GT-64120A only */
116 #define GT_ECC_ERRDATAHI 0x484 /* GT-64120A only */
117 #define GT_ECC_MEM 0x488 /* GT-64120A only */
118 #define GT_ECC_CALC 0x48c /* GT-64120A only */
119 #define GT_ECC_ERRADDR 0x490 /* GT-64120A only */
122 #define GT_DMA0_CNT_OFS 0x800
123 #define GT_DMA1_CNT_OFS 0x804
124 #define GT_DMA2_CNT_OFS 0x808
125 #define GT_DMA3_CNT_OFS 0x80c
126 #define GT_DMA0_SA_OFS 0x810
127 #define GT_DMA1_SA_OFS 0x814
128 #define GT_DMA2_SA_OFS 0x818
129 #define GT_DMA3_SA_OFS 0x81c
130 #define GT_DMA0_DA_OFS 0x820
131 #define GT_DMA1_DA_OFS 0x824
132 #define GT_DMA2_DA_OFS 0x828
133 #define GT_DMA3_DA_OFS 0x82c
134 #define GT_DMA0_NEXT_OFS 0x830
135 #define GT_DMA1_NEXT_OFS 0x834
136 #define GT_DMA2_NEXT_OFS 0x838
137 #define GT_DMA3_NEXT_OFS 0x83c
139 #define GT_DMA0_CUR_OFS 0x870
140 #define GT_DMA1_CUR_OFS 0x874
141 #define GT_DMA2_CUR_OFS 0x878
142 #define GT_DMA3_CUR_OFS 0x87c
145 #define GT_DMA0_CTRL_OFS 0x840
146 #define GT_DMA1_CTRL_OFS 0x844
147 #define GT_DMA2_CTRL_OFS 0x848
148 #define GT_DMA3_CTRL_OFS 0x84c
151 #define GT_DMA_ARB_OFS 0x860
154 #define GT_TC0_OFS 0x850
155 #define GT_TC1_OFS 0x854
156 #define GT_TC2_OFS 0x858
157 #define GT_TC3_OFS 0x85c
159 #define GT_TC_CONTROL_OFS 0x864
162 #define GT_PCI0_CMD_OFS 0xc00
163 #define GT_PCI0_TOR_OFS 0xc04
164 #define GT_PCI0_BS_SCS10_OFS 0xc08
165 #define GT_PCI0_BS_SCS32_OFS 0xc0c
166 #define GT_PCI0_BS_CS20_OFS 0xc10
167 #define GT_PCI0_BS_CS3BT_OFS 0xc14
169 #define GT_PCI1_IACK_OFS 0xc30
170 #define GT_PCI0_IACK_OFS 0xc34
172 #define GT_PCI0_BARE_OFS 0xc3c
173 #define GT_PCI0_PREFMBR_OFS 0xc40
175 #define GT_PCI0_SCS10_BAR_OFS 0xc48
176 #define GT_PCI0_SCS32_BAR_OFS 0xc4c
177 #define GT_PCI0_CS20_BAR_OFS 0xc50
178 #define GT_PCI0_CS3BT_BAR_OFS 0xc54
179 #define GT_PCI0_SSCS10_BAR_OFS 0xc58
180 #define GT_PCI0_SSCS32_BAR_OFS 0xc5c
182 #define GT_PCI0_SCS3BT_BAR_OFS 0xc64
184 #define GT_PCI1_CMD_OFS 0xc80
185 #define GT_PCI1_TOR_OFS 0xc84
186 #define GT_PCI1_BS_SCS10_OFS 0xc88
187 #define GT_PCI1_BS_SCS32_OFS 0xc8c
188 #define GT_PCI1_BS_CS20_OFS 0xc90
189 #define GT_PCI1_BS_CS3BT_OFS 0xc94
191 #define GT_PCI1_BARE_OFS 0xcbc
192 #define GT_PCI1_PREFMBR_OFS 0xcc0
194 #define GT_PCI1_SCS10_BAR_OFS 0xcc8
195 #define GT_PCI1_SCS32_BAR_OFS 0xccc
196 #define GT_PCI1_CS20_BAR_OFS 0xcd0
197 #define GT_PCI1_CS3BT_BAR_OFS 0xcd4
198 #define GT_PCI1_SSCS10_BAR_OFS 0xcd8
199 #define GT_PCI1_SSCS32_BAR_OFS 0xcdc
201 #define GT_PCI1_SCS3BT_BAR_OFS 0xce4
203 #define GT_PCI1_CFGADDR_OFS 0xcf0
204 #define GT_PCI1_CFGDATA_OFS 0xcf4
205 #define GT_PCI0_CFGADDR_OFS 0xcf8
206 #define GT_PCI0_CFGDATA_OFS 0xcfc
209 #define GT_INTRCAUSE_OFS 0xc18
210 #define GT_INTRMASK_OFS 0xc1c
212 #define GT_PCI0_ICMASK_OFS 0xc24
213 #define GT_PCI0_SERR0MASK_OFS 0xc28
215 #define GT_CPU_INTSEL_OFS 0xc70
216 #define GT_PCI0_INTSEL_OFS 0xc74
218 #define GT_HINTRCAUSE_OFS 0xc98
219 #define GT_HINTRMASK_OFS 0xc9c
221 #define GT_PCI0_HICMASK_OFS 0xca4
222 #define GT_PCI1_SERR1MASK_OFS 0xca8
228 #define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010
229 #define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014
230 #define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018
231 #define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01c
232 #define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020
233 #define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024
234 #define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028
235 #define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02c
236 #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030
237 #define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034
238 #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040
239 #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044
240 #define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050
241 #define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054
242 #define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060
243 #define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064
244 #define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068
245 #define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06c
246 #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070
247 #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074
248 #define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078
249 #define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07c
251 #define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c10
252 #define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c14
253 #define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c18
254 #define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c1c
255 #define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c20
256 #define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c24
257 #define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c28
258 #define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c2c
259 #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c30
260 #define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c34
261 #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c40
262 #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c44
263 #define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1c50
264 #define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1c54
265 #define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c60
266 #define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c64
267 #define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c68
268 #define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c6c
269 #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c70
270 #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c74
271 #define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c78
272 #define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c7c
283 #define GT_CPU_WR_DXDXDXDX 0
288 #define GT_PCI_LD_SHF 0
290 #define GT_PCI_HD_SHF 0
292 #define GT_PCI_REMAP_SHF 0
317 #define GT_SDRAM_BM_ORDER_LIN 0
319 #define GT_SDRAM_BM_RSVD_ALL1 0xffb
322 #define GT_SDRAM_ADDRDECODE_ADDR_SHF 0
324 #define GT_SDRAM_ADDRDECODE_ADDR_0 0
334 #define GT_SDRAM_B0_CASLAT_SHF 0
346 #define GT_SDRAM_B0_SRASPRCHG_2 0
356 #define GT_SDRAM_B0_64BITINT_2 0
362 #define GT_SDRAM_B0_BW_32 0
380 #define GT_SDRAM_B0_SRAS2SCAS_2 0
386 #define GT_SDRAM_B0_SIZE_16M 0
396 #define GT_SDRAM_B0_BLEN_8 0
400 #define GT_SDRAM_CFG_REFINT_SHF 0
431 #define GT_SDRAM_OPMODE_OP_SHF 0
433 #define GT_SDRAM_OPMODE_OP_NORMAL 0
439 #define GT_TC_CONTROL_ENTC0_SHF 0
447 #define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0
506 #define GT_PCI0_CMD_MBYTESWAP_SHF 0
529 #define GT_DEF_PCI0_IO_BASE 0x10000000
530 #define GT_DEF_PCI0_IO_SIZE 0x02000000
531 #define GT_DEF_PCI0_MEM0_BASE 0x12000000
532 #define GT_DEF_PCI0_MEM0_SIZE 0x02000000
533 #define GT_DEF_BASE 0x14000000