Home
last modified time | relevance | path

Searched +full:0 +full:x80040000 (Results 1 – 25 of 37) sorted by relevance

12

/openbmc/u-boot/arch/m68k/cpu/mcf5227x/
H A Dstart.S16 move.w #0x2700,%sr; /* disable intrs */ \
40 INITSP: .long 0 /* Initial SP */
43 INITSP: .long 0 /* Initial SP */
59 /* TRAP #0 - #15 */
103 .long 0x00000000 /* checksum, not yet implemented */
104 .long 0x00020000 /* image length */
115 move.l #0xFC008000, %a1
117 move.l #0xFC008008, %a1
119 move.l #0xFC008004, %a1
126 move.l #0xFC0A4074, %a1
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mxs/
H A Dregs-base.h21 #define MXS_ICOLL_BASE 0x80000000
22 #define MXS_APBH_BASE 0x80004000
23 #define MXS_ECC8_BASE 0x80008000
24 #define MXS_BCH_BASE 0x8000A000
25 #define MXS_GPMI_BASE 0x8000C000
26 #define MXS_SSP0_BASE 0x80010000
27 #define MXS_SSP1_BASE 0x80034000
28 #define MXS_ETM_BASE 0x80014000
29 #define MXS_PINCTRL_BASE 0x80018000
30 #define MXS_DIGCTL_BASE 0x8001C000
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_3_0_default.h27 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
28 #define mmSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
29 #define mmSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
32 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
33 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
34 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
35 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
36 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dimx23-clock.yaml19 ref_xtal 0
83 reg = <0x80040000 0x2000>;
H A Dimx28-clock.yaml19 ref_xtal 0
106 reg = <0x80040000 0x2000>;
/openbmc/linux/arch/arm/boot/dts/alphascale/
H A Dalphascale-asm9260.dtsi16 reg = <0x20000000 0x2000000>;
20 #address-cells = <0>;
21 #size-cells = <0>;
32 #clock-cells = <0>;
47 reg = <0x80040000 0x204>;
54 reg = <0x80054000 0x200>;
59 reg = <0x80088000 0x4000>;
/openbmc/u-boot/board/freescale/ls1043ardb/
H A Dddr.h31 * memory controller 0
36 {1, 1666, 0, 12, 7, 0x07090800, 0x00000000,},
37 {1, 1900, 0, 12, 7, 0x07090800, 0x00000000,},
38 {1, 2200, 0, 12, 7, 0x07090800, 0x00000000,},
49 .cs[0].bnds = 0x0000007F,
50 .cs[1].bnds = 0,
51 .cs[2].bnds = 0,
52 .cs[3].bnds = 0,
53 .cs[0].config = 0x80040322,
54 .cs[0].config_2 = 0,
[all …]
/openbmc/u-boot/include/configs/
H A Dls1021aiot.h28 #define DDR_SDRAM_CFG 0x470c0008
29 #define DDR_CS0_BNDS 0x008000bf
30 #define DDR_CS0_CONFIG 0x80014302
31 #define DDR_TIMING_CFG_0 0x50550004
32 #define DDR_TIMING_CFG_1 0xbcb38c56
33 #define DDR_TIMING_CFG_2 0x0040d120
34 #define DDR_TIMING_CFG_3 0x010e1000
35 #define DDR_TIMING_CFG_4 0x00000001
36 #define DDR_TIMING_CFG_5 0x03401400
37 #define DDR_SDRAM_CFG_2 0x00401010
[all …]
H A Dls1021atwr.h29 #define DDR_SDRAM_CFG 0x470c0008
30 #define DDR_CS0_BNDS 0x008000bf
31 #define DDR_CS0_CONFIG 0x80014302
32 #define DDR_TIMING_CFG_0 0x50550004
33 #define DDR_TIMING_CFG_1 0xbcb38c56
34 #define DDR_TIMING_CFG_2 0x0040d120
35 #define DDR_TIMING_CFG_3 0x010e1000
36 #define DDR_TIMING_CFG_4 0x00000001
37 #define DDR_TIMING_CFG_5 0x03401400
38 #define DDR_SDRAM_CFG_2 0x00401010
[all …]
H A DMPC8569MDS.h52 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
53 #define CONFIG_SYS_MEMTEST_END 0x00400000
58 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
63 #define CONFIG_SYS_CCSRBAR 0xe0000000
75 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
77 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
85 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
89 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
90 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
91 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A DkuroboxHG.dts37 #size-cells = <0>;
41 reg = <0x0>;
44 bus-frequency = <0>; /* Fixed by bootloader */
46 i-cache-size = <0x4000>;
47 d-cache-size = <0x4000>;
53 reg = <0x0 0x8000000>;
61 store-gathering = <0>; /* 0 == off, !0 == on */
62 reg = <0x80000000 0x100000>;
63 ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */
64 0xfc000000 0xfc000000 0x100000 /* EUMB */
[all …]
H A DkuroboxHD.dts37 #size-cells = <0>;
41 reg = <0x0>;
44 bus-frequency = <0>; /* Fixed by bootloader */
46 i-cache-size = <0x4000>;
47 d-cache-size = <0x4000>;
53 reg = <0x0 0x4000000>;
61 store-gathering = <0>; /* 0 == off, !0 == on */
62 reg = <0x80000000 0x100000>;
63 ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */
64 0xfc000000 0xfc000000 0x100000 /* EUMB */
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx23.dtsi32 #size-cells = <0>;
34 cpu@0 {
37 reg = <0>;
45 reg = <0x80000000 0x80000>;
52 reg = <0x80000000 0x40000>;
59 reg = <0x80000000 0x2000>;
64 reg = <0x80004000 0x2000>;
65 interrupts = <0>, <14>, <20>, <0>,
73 reg = <0x80008000 0x2000>;
81 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
[all …]
H A Dimx28.dtsi43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0>;
56 reg = <0x80000000 0x80000>;
63 reg = <0x80000000 0x3c900>;
70 reg = <0x80000000 0x2000>;
74 reg = <0x80002000 0x2000>;
83 reg = <0x80004000 0x2000>;
87 <87>, <86>, <0>, <0>;
94 reg = <0x80006000 0x800>;
[all …]
/openbmc/linux/include/uapi/linux/
H A Didxd.h14 IDXD_SCMD_DEV_ENABLED = 0x80000010,
15 IDXD_SCMD_DEV_NOT_ENABLED = 0x80000020,
16 IDXD_SCMD_WQ_ENABLED = 0x80000021,
17 IDXD_SCMD_DEV_DMA_ERR = 0x80020000,
18 IDXD_SCMD_WQ_NO_GRP = 0x80030000,
19 IDXD_SCMD_WQ_NO_NAME = 0x80040000,
20 IDXD_SCMD_WQ_NO_SVM = 0x80050000,
21 IDXD_SCMD_WQ_NO_THRESH = 0x80060000,
22 IDXD_SCMD_WQ_PORTAL_ERR = 0x80070000,
23 IDXD_SCMD_WQ_RES_ALLOC_ERR = 0x80080000,
[all …]
/openbmc/u-boot/drivers/ram/mediatek/
H A Dddr3-mt7629.c17 #define EMI_CONA 0x000
18 #define EMI_CONF 0x028
19 #define EMI_CONM 0x060
22 #define DDRPHY_PLL1 0x0000
23 #define DDRPHY_PLL2 0x0004
24 #define DDRPHY_PLL3 0x0008
25 #define DDRPHY_PLL4 0x000c
26 #define DDRPHY_PLL5 0x0010
27 #define DDRPHY_PLL7 0x0018
28 #define DDRPHY_B0_DLL_ARPI0 0x0080
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-ep93xx/
H A Dep93xx.h24 #define EP93XX_AHB_BASE 0x80000000
25 #define EP93XX_APB_BASE 0x80800000
28 * 0x80000000 - 0x8000FFFF: DMA
30 #define DMA_OFFSET 0x000000
73 * 0x80010000 - 0x8001FFFF: Ethernet MAC
75 #define MAC_OFFSET 0x010000
155 #define SELFCTL_RESET (1 << 0)
186 #define BMCTL_RXEN (1 << 0)
191 #define BMSTS_QID_MASK 0x07
192 #define BMSTS_QID_RXDATA 0x00
[all …]
/openbmc/linux/arch/powerpc/kernel/
H A Dcpu_specs_book3s_32.h12 .pvr_mask = 0xffff0000,
13 .pvr_value = 0x00030000,
17 .mmu_features = 0,
25 .pvr_mask = 0xffff0000,
26 .pvr_value = 0x00060000,
30 .mmu_features = 0,
38 .pvr_mask = 0xffff0000,
39 .pvr_value = 0x00070000,
43 .mmu_features = 0,
51 .pvr_mask = 0x7fff0000,
[all …]
/openbmc/u-boot/cmd/
H A Dtsi148.c43 busdevfn = pci_find_device(LPCI_VENDOR, LPCI_DEVICE, 0); in tsi148_init()
50 pci_write_config_dword(busdevfn, 0x0c, 0); in tsi148_init()
58 memset(dev, 0, sizeof(*dev)); in tsi148_init()
62 val &= ~0xf; in tsi148_init()
82 for (j = 0; j < 8; j++) { in tsi148_init()
83 __raw_writel(htonl(0x00000000), &dev->uregs->outbound[j].otat); in tsi148_init()
84 __raw_writel(htonl(0x00000000), &dev->uregs->inbound[j].itat); in tsi148_init()
88 __raw_writel(htonl(0x00000084), &dev->uregs->vctrl); in tsi148_init()
91 if ((__raw_readl(&dev->uregs->vstat) & 0x00000100) != 0) in tsi148_init()
101 __raw_writel(htonl(0x00000000), &dev->uregs->inten); in tsi148_init()
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723be/
H A Dtable.c8 0x800, 0x80040000,
9 0x804, 0x00000003,
10 0x808, 0x0000FC00,
11 0x80C, 0x0000000A,
12 0x810, 0x10001331,
13 0x814, 0x020C3D10,
14 0x818, 0x02200385,
15 0x81C, 0x00000000,
16 0x820, 0x01000100,
17 0x824, 0x00190204,
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/
H A Dtable.c6 0x800, 0x80040000,
7 0x804, 0x00000003,
8 0x808, 0x0000FC00,
9 0x80C, 0x0000000A,
10 0x810, 0x10001331,
11 0x814, 0x020C3D10,
12 0x818, 0x02200385,
13 0x81C, 0x00000000,
14 0x820, 0x01000100,
15 0x824, 0x00390204,
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
H A Dtable.c7 0x800, 0x80040000,
8 0x804, 0x00000003,
9 0x808, 0x0000fc00,
10 0x80c, 0x0000000a,
11 0x810, 0x10005388,
12 0x814, 0x020c3d10,
13 0x818, 0x02200385,
14 0x81c, 0x00000000,
15 0x820, 0x01000100,
16 0x824, 0x00390004,
[all …]
/openbmc/linux/drivers/staging/rtl8723bs/hal/
H A DHalHWImg8723B_BB.c16 ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */ in CheckPositive()
31 pDM_Odm->TypeGLNA << 0 | in CheckPositive()
40 if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) in CheckPositive()
42 if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) in CheckPositive()
48 cond1 &= 0x000F0FFF; in CheckPositive()
49 driver1 &= 0x000F0FFF; in CheckPositive()
52 u32 bitMask = 0; in CheckPositive()
54 if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE */ in CheckPositive()
57 if ((cond1 & BIT0) != 0) /* GLNA */ in CheckPositive()
58 bitMask |= 0x000000FF; in CheckPositive()
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
H A Dtable.c6 0x800, 0x80040000,
7 0x804, 0x00000003,
8 0x808, 0x0000FC00,
9 0x80C, 0x0000000A,
10 0x810, 0x10001331,
11 0x814, 0x020C3D10,
12 0x818, 0x02220385,
13 0x81C, 0x00000000,
14 0x820, 0x01000100,
15 0x824, 0x00390204,
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/
H A Dtable.c7 0x024, 0x0011800f,
8 0x028, 0x00ffdb83,
9 0x800, 0x80040002,
10 0x804, 0x00000003,
11 0x808, 0x0000fc00,
12 0x80c, 0x0000000a,
13 0x810, 0x10000330,
14 0x814, 0x020c3d10,
15 0x818, 0x02200385,
16 0x81c, 0x00000000,
[all …]

12