Lines Matching +full:0 +full:x80040000
17 #define EMI_CONA 0x000
18 #define EMI_CONF 0x028
19 #define EMI_CONM 0x060
22 #define DDRPHY_PLL1 0x0000
23 #define DDRPHY_PLL2 0x0004
24 #define DDRPHY_PLL3 0x0008
25 #define DDRPHY_PLL4 0x000c
26 #define DDRPHY_PLL5 0x0010
27 #define DDRPHY_PLL7 0x0018
28 #define DDRPHY_B0_DLL_ARPI0 0x0080
29 #define DDRPHY_B0_DLL_ARPI1 0x0084
30 #define DDRPHY_B0_DLL_ARPI2 0x0088
31 #define DDRPHY_B0_DLL_ARPI3 0x008c
32 #define DDRPHY_B0_DLL_ARPI4 0x0090
33 #define DDRPHY_B0_DLL_ARPI5 0x0094
34 #define DDRPHY_B0_DQ2 0x00a0
35 #define DDRPHY_B0_DQ3 0x00a4
36 #define DDRPHY_B0_DQ4 0x00a8
37 #define DDRPHY_B0_DQ5 0x00ac
38 #define DDRPHY_B0_DQ6 0x00b0
39 #define DDRPHY_B0_DQ7 0x00b4
40 #define DDRPHY_B0_DQ8 0x00b8
41 #define DDRPHY_B1_DLL_ARPI0 0x0100
42 #define DDRPHY_B1_DLL_ARPI1 0x0104
43 #define DDRPHY_B1_DLL_ARPI2 0x0108
44 #define DDRPHY_B1_DLL_ARPI3 0x010c
45 #define DDRPHY_B1_DLL_ARPI4 0x0110
46 #define DDRPHY_B1_DLL_ARPI5 0x0114
47 #define DDRPHY_B1_DQ2 0x0120
48 #define DDRPHY_B1_DQ3 0x0124
49 #define DDRPHY_B1_DQ4 0x0128
50 #define DDRPHY_B1_DQ5 0x012c
51 #define DDRPHY_B1_DQ6 0x0130
52 #define DDRPHY_B1_DQ7 0x0134
53 #define DDRPHY_B1_DQ8 0x0138
54 #define DDRPHY_CA_DLL_ARPI0 0x0180
55 #define DDRPHY_CA_DLL_ARPI1 0x0184
56 #define DDRPHY_CA_DLL_ARPI2 0x0188
57 #define DDRPHY_CA_DLL_ARPI3 0x018c
58 #define DDRPHY_CA_DLL_ARPI4 0x0190
59 #define DDRPHY_CA_DLL_ARPI5 0x0194
60 #define DDRPHY_CA_CMD2 0x01a0
61 #define DDRPHY_CA_CMD3 0x01a4
62 #define DDRPHY_CA_CMD5 0x01ac
63 #define DDRPHY_CA_CMD6 0x01b0
64 #define DDRPHY_CA_CMD7 0x01b4
65 #define DDRPHY_CA_CMD8 0x01b8
66 #define DDRPHY_MISC_VREF_CTRL 0x0264
67 #define DDRPHY_MISC_IMP_CTRL0 0x0268
68 #define DDRPHY_MISC_IMP_CTRL1 0x026c
69 #define DDRPHY_MISC_SHU_OPT 0x0270
70 #define DDRPHY_MISC_SPM_CTRL0 0x0274
71 #define DDRPHY_MISC_SPM_CTRL1 0x0278
72 #define DDRPHY_MISC_SPM_CTRL2 0x027c
73 #define DDRPHY_MISC_CG_CTRL0 0x0284
74 #define DDRPHY_MISC_CG_CTRL1 0x0288
75 #define DDRPHY_MISC_CG_CTRL2 0x028c
76 #define DDRPHY_MISC_CG_CTRL4 0x0294
77 #define DDRPHY_MISC_CTRL0 0x029c
78 #define DDRPHY_MISC_CTRL1 0x02a0
79 #define DDRPHY_MISC_CTRL3 0x02a8
80 #define DDRPHY_MISC_RXDVS1 0x05e4
81 #define DDRPHY_SHU1_B0_DQ4 0x0c10
82 #define DDRPHY_SHU1_B0_DQ5 0x0c14
83 #define DDRPHY_SHU1_B0_DQ6 0x0c18
84 #define DDRPHY_SHU1_B0_DQ7 0x0c1c
85 #define DDRPHY_SHU1_B1_DQ4 0x0c90
86 #define DDRPHY_SHU1_B1_DQ5 0x0c94
87 #define DDRPHY_SHU1_B1_DQ6 0x0c98
88 #define DDRPHY_SHU1_B1_DQ7 0x0c9c
89 #define DDRPHY_SHU1_CA_CMD2 0x0d08
90 #define DDRPHY_SHU1_CA_CMD4 0x0d10
91 #define DDRPHY_SHU1_CA_CMD5 0x0d14
92 #define DDRPHY_SHU1_CA_CMD6 0x0d18
93 #define DDRPHY_SHU1_CA_CMD7 0x0d1c
94 #define DDRPHY_SHU1_PLL0 0x0d80
95 #define DDRPHY_SHU1_PLL1 0x0d84
96 #define DDRPHY_SHU1_PLL4 0x0d90
97 #define DDRPHY_SHU1_PLL5 0x0d94
98 #define DDRPHY_SHU1_PLL6 0x0d98
99 #define DDRPHY_SHU1_PLL7 0x0d9C
100 #define DDRPHY_SHU1_PLL8 0x0da0
101 #define DDRPHY_SHU1_PLL9 0x0da4
102 #define DDRPHY_SHU1_PLL10 0x0da8
103 #define DDRPHY_SHU1_PLL11 0x0dac
104 #define DDRPHY_SHU1_R0_B0_DQ2 0x0e08
105 #define DDRPHY_SHU1_R0_B0_DQ3 0x0e0c
106 #define DDRPHY_SHU1_R0_B0_DQ4 0x0e10
107 #define DDRPHY_SHU1_R0_B0_DQ5 0x0e14
108 #define DDRPHY_SHU1_R0_B0_DQ6 0x0e18
109 #define DDRPHY_SHU1_R0_B0_DQ7 0x0e1c
110 #define DDRPHY_SHU1_R0_B1_DQ2 0x0e58
111 #define DDRPHY_SHU1_R0_B1_DQ3 0x0e5c
112 #define DDRPHY_SHU1_R0_B1_DQ4 0x0e60
113 #define DDRPHY_SHU1_R0_B1_DQ5 0x0e64
114 #define DDRPHY_SHU1_R0_B1_DQ6 0x0e68
115 #define DDRPHY_SHU1_R0_B1_DQ7 0x0e6c
116 #define DDRPHY_SHU1_R0_CA_CMD9 0x0ec4
117 #define DDRPHY_SHU1_R1_B0_DQ2 0x0f08
118 #define DDRPHY_SHU1_R1_B0_DQ3 0x0f0c
119 #define DDRPHY_SHU1_R1_B0_DQ4 0x0f10
120 #define DDRPHY_SHU1_R1_B0_DQ5 0x0f14
121 #define DDRPHY_SHU1_R1_B0_DQ6 0x0f18
122 #define DDRPHY_SHU1_R1_B0_DQ7 0x0f1c
123 #define DDRPHY_SHU1_R1_B1_DQ2 0x0f58
124 #define DDRPHY_SHU1_R1_B1_DQ3 0x0f5c
125 #define DDRPHY_SHU1_R1_B1_DQ4 0x0f60
126 #define DDRPHY_SHU1_R1_B1_DQ5 0x0f64
127 #define DDRPHY_SHU1_R1_B1_DQ6 0x0f68
128 #define DDRPHY_SHU1_R1_B1_DQ7 0x0f6c
129 #define DDRPHY_SHU1_R1_CA_CMD9 0x0fc4
132 #define DRAMC_DDRCONF0 0x0000
133 #define DRAMC_DRAMCTRL 0x0004
134 #define DRAMC_MISCTL0 0x0008
135 #define DRAMC_PERFCTL0 0x000c
136 #define DRAMC_ARBCTL 0x0010
137 #define DRAMC_RSTMASK 0x001c
138 #define DRAMC_PADCTRL 0x0020
139 #define DRAMC_CKECTRL 0x0024
140 #define DRAMC_RKCFG 0x0034
141 #define DRAMC_DRAMC_PD_CTRL 0x0038
142 #define DRAMC_CLKAR 0x003c
143 #define DRAMC_CLKCTRL 0x0040
144 #define DRAMC_SREFCTRL 0x0048
145 #define DRAMC_REFCTRL0 0x004c
146 #define DRAMC_REFCTRL1 0x0050
147 #define DRAMC_REFRATRE_FILTER 0x0054
148 #define DRAMC_ZQCS 0x0058
149 #define DRAMC_MRS 0x005c
150 #define DRAMC_SPCMD 0x0060
151 #define DRAMC_SPCMDCTRL 0x0064
152 #define DRAMC_HW_MRR_FUN 0x0074
153 #define DRAMC_TEST2_1 0x0094
154 #define DRAMC_TEST2_2 0x0098
155 #define DRAMC_TEST2_3 0x009c
156 #define DRAMC_TEST2_4 0x00a0
157 #define DRAMC_CATRAINING1 0x00b0
158 #define DRAMC_DUMMY_RD 0x00d0
159 #define DRAMC_SHUCTRL 0x00d4
160 #define DRAMC_SHUCTRL2 0x00dc
161 #define DRAMC_STBCAL 0x0200
162 #define DRAMC_STBCAL1 0x0204
163 #define DRAMC_EYESCAN 0x020c
164 #define DRAMC_DVFSDLL 0x0210
165 #define DRAMC_SHU_ACTIM0 0x0800
166 #define DRAMC_SHU_ACTIM1 0x0804
167 #define DRAMC_SHU_ACTIM2 0x0808
168 #define DRAMC_SHU_ACTIM3 0x080c
169 #define DRAMC_SHU_ACTIM4 0x0810
170 #define DRAMC_SHU_ACTIM5 0x0814
171 #define DRAMC_SHU_ACTIM_XRT 0x081c
172 #define DRAMC_SHU_AC_TIME_05T 0x0820
173 #define DRAMC_SHU_CONF0 0x0840
174 #define DRAMC_SHU_CONF1 0x0844
175 #define DRAMC_SHU_CONF2 0x0848
176 #define DRAMC_SHU_CONF3 0x084c
177 #define DRAMC_SHU_RANKCTL 0x0858
178 #define DRAMC_SHU_CKECTRL 0x085c
179 #define DRAMC_SHU_ODTCTRL 0x0860
180 #define DRAMC_SHU_PIPE 0x0878
181 #define DRAMC_SHU_SELPH_CA1 0x0880
182 #define DRAMC_SHU_SELPH_CA2 0x0884
183 #define DRAMC_SHU_SELPH_CA3 0x0888
184 #define DRAMC_SHU_SELPH_CA4 0x088c
185 #define DRAMC_SHU_SELPH_CA5 0x0890
186 #define DRAMC_SHU_SELPH_CA6 0x0894
187 #define DRAMC_SHU_SELPH_CA7 0x0898
188 #define DRAMC_SHU_SELPH_CA8 0x089c
189 #define DRAMC_SHU_SELPH_DQS0 0x08a0
190 #define DRAMC_SHU_SELPH_DQS1 0x08a4
191 #define DRAMC_SHU1_DRVING1 0x08a8
192 #define DRAMC_SHU1_DRVING2 0x08ac
193 #define DRAMC_SHU1_WODT 0x08c0
194 #define DRAMC_SHU_SCINTV 0x08c8
195 #define DRAMC_SHURK0_DQSCTL 0x0a00
196 #define DRAMC_SHURK0_DQSIEN 0x0a04
197 #define DRAMC_SHURK0_SELPH_ODTEN0 0x0a1c
198 #define DRAMC_SHURK0_SELPH_ODTEN1 0x0a20
199 #define DRAMC_SHURK0_SELPH_DQSG0 0x0a24
200 #define DRAMC_SHURK0_SELPH_DQSG1 0x0a28
201 #define DRAMC_SHURK0_SELPH_DQ0 0x0a2c
202 #define DRAMC_SHURK0_SELPH_DQ1 0x0a30
203 #define DRAMC_SHURK0_SELPH_DQ2 0x0a34
204 #define DRAMC_SHURK0_SELPH_DQ3 0x0a38
205 #define DRAMC_SHURK1_DQSCTL 0x0b00
206 #define DRAMC_SHURK1_SELPH_ODTEN0 0x0b1c
207 #define DRAMC_SHURK1_SELPH_ODTEN1 0x0b20
208 #define DRAMC_SHURK1_SELPH_DQSG0 0x0b24
209 #define DRAMC_SHURK1_SELPH_DQSG1 0x0b28
210 #define DRAMC_SHURK1_SELPH_DQ0 0x0b2c
211 #define DRAMC_SHURK1_SELPH_DQ1 0x0b30
212 #define DRAMC_SHURK1_SELPH_DQ2 0x0b34
213 #define DRAMC_SHURK1_SELPH_DQ3 0x0b38
214 #define DRAMC_SHURK2_SELPH_ODTEN0 0x0c1c
215 #define DRAMC_SHURK2_SELPH_ODTEN1 0x0c20
216 #define DRAMC_SHU_DQSG_RETRY 0x0c54
220 #define WALKING_PATTERN 0x12345678
221 #define WALKING_STEP 0x4000000
249 for (step = 0; step < 5; step++) { in mtk_ddr3_rank_size_detect()
263 return 0; in mtk_ddr3_rank_size_detect()
276 writel(0x00003010, priv->emi + EMI_CONA); in mtk_ddr3_init()
277 writel(0x00000000, priv->emi + EMI_CONF); in mtk_ddr3_init()
278 writel(0x000006b8, priv->emi + EMI_CONM); in mtk_ddr3_init()
280 writel(0x20c00, priv->dramc_ao + DRAMC_SHU1_DRVING1); in mtk_ddr3_init()
282 writel(0x8320c83, priv->dramc_ao + DRAMC_SHU1_DRVING2); in mtk_ddr3_init()
285 writel(0x2201, priv->dramc_ao + DRAMC_DRAMCTRL); in mtk_ddr3_init()
286 writel(0x3000000c, priv->dramc_ao + DRAMC_CLKCTRL); in mtk_ddr3_init()
287 writel(0xe08, priv->ddrphy + DDRPHY_CA_CMD5); in mtk_ddr3_init()
288 writel(0x60e, priv->ddrphy + DDRPHY_SHU1_CA_CMD5); in mtk_ddr3_init()
289 writel(0x0, priv->ddrphy + DDRPHY_MISC_SPM_CTRL1); in mtk_ddr3_init()
290 writel(0xffffffff, priv->ddrphy + DDRPHY_MISC_SPM_CTRL0); in mtk_ddr3_init()
291 writel(0xffffffff, priv->ddrphy + DDRPHY_MISC_SPM_CTRL2); in mtk_ddr3_init()
292 writel(0x6003bf, priv->ddrphy + DDRPHY_MISC_CG_CTRL2); in mtk_ddr3_init()
293 writel(0x13300000, priv->ddrphy + DDRPHY_MISC_CG_CTRL4); in mtk_ddr3_init()
295 writel(0x1, priv->ddrphy + DDRPHY_SHU1_CA_CMD7); in mtk_ddr3_init()
296 writel(0x21, priv->ddrphy + DDRPHY_SHU1_B0_DQ7); in mtk_ddr3_init()
297 writel(0x1, priv->ddrphy + DDRPHY_SHU1_B1_DQ7); in mtk_ddr3_init()
298 writel(0xfff0, priv->ddrphy + DDRPHY_CA_CMD2); in mtk_ddr3_init()
299 writel(0x0, priv->ddrphy + DDRPHY_B0_DQ2); in mtk_ddr3_init()
300 writel(0x0, priv->ddrphy + DDRPHY_B1_DQ2); in mtk_ddr3_init()
301 writel(0x7, priv->ddrphy + DDRPHY_MISC_RXDVS1); in mtk_ddr3_init()
302 writel(0x10, priv->ddrphy + DDRPHY_PLL3); in mtk_ddr3_init()
303 writel(0x8e8e0000, priv->ddrphy + DDRPHY_MISC_VREF_CTRL); in mtk_ddr3_init()
304 writel(0x2e0040, priv->ddrphy + DDRPHY_MISC_IMP_CTRL0); in mtk_ddr3_init()
305 writel(0x50060e, priv->ddrphy + DDRPHY_SHU1_B0_DQ5); in mtk_ddr3_init()
306 writel(0x50060e, priv->ddrphy + DDRPHY_SHU1_B1_DQ5); in mtk_ddr3_init()
309 writel(0x10, priv->ddrphy + DDRPHY_B0_DQ3); in mtk_ddr3_init()
310 writel(0x10, priv->ddrphy + DDRPHY_B1_DQ3); in mtk_ddr3_init()
311 writel(0x3f600, priv->ddrphy + DDRPHY_MISC_CG_CTRL1); in mtk_ddr3_init()
312 writel(0x1010, priv->ddrphy + DDRPHY_B0_DQ4); in mtk_ddr3_init()
313 writel(0x1110e0e, priv->ddrphy + DDRPHY_B0_DQ5); in mtk_ddr3_init()
314 writel(0x10c10d0, priv->ddrphy + DDRPHY_B0_DQ6); in mtk_ddr3_init()
315 writel(0x3110e0e, priv->ddrphy + DDRPHY_B0_DQ5); in mtk_ddr3_init()
316 writel(0x1010, priv->ddrphy + DDRPHY_B1_DQ4); in mtk_ddr3_init()
317 writel(0x1110e0e, priv->ddrphy + DDRPHY_B1_DQ5); in mtk_ddr3_init()
318 writel(0x10c10d0, priv->ddrphy + DDRPHY_B1_DQ6); in mtk_ddr3_init()
319 writel(0x3110e0e, priv->ddrphy + DDRPHY_B1_DQ5); in mtk_ddr3_init()
320 writel(0x7fffffc, priv->ddrphy + DDRPHY_CA_CMD3); in mtk_ddr3_init()
321 writel(0xc0010, priv->ddrphy + DDRPHY_CA_CMD6); in mtk_ddr3_init()
322 writel(0x101, priv->ddrphy + DDRPHY_SHU1_CA_CMD2); in mtk_ddr3_init()
323 writel(0x41e, priv->ddrphy + DDRPHY_B0_DQ3); in mtk_ddr3_init()
324 writel(0x41e, priv->ddrphy + DDRPHY_B1_DQ3); in mtk_ddr3_init()
325 writel(0x180101, priv->ddrphy + DDRPHY_CA_CMD8); in mtk_ddr3_init()
326 writel(0x0, priv->ddrphy + DDRPHY_MISC_IMP_CTRL1); in mtk_ddr3_init()
327 writel(0x11400000, priv->ddrphy + DDRPHY_MISC_CG_CTRL4); in mtk_ddr3_init()
328 writel(0xfff0f0f0, priv->ddrphy + DDRPHY_MISC_SHU_OPT); in mtk_ddr3_init()
329 writel(0x1f, priv->ddrphy + DDRPHY_MISC_CG_CTRL0); in mtk_ddr3_init()
331 writel(0x0, priv->ddrphy + DDRPHY_SHU1_CA_CMD6); in mtk_ddr3_init()
332 writel(0x0, priv->ddrphy + DDRPHY_SHU1_B0_DQ6); in mtk_ddr3_init()
333 writel(0x0, priv->ddrphy + DDRPHY_SHU1_B1_DQ6); in mtk_ddr3_init()
334 writel(0x40000, priv->ddrphy + DDRPHY_PLL4); in mtk_ddr3_init()
335 writel(0x0, priv->ddrphy + DDRPHY_PLL1); in mtk_ddr3_init()
336 writel(0x0, priv->ddrphy + DDRPHY_PLL2); in mtk_ddr3_init()
337 writel(0x666008, priv->ddrphy + DDRPHY_CA_DLL_ARPI5); in mtk_ddr3_init()
338 writel(0x80666008, priv->ddrphy + DDRPHY_B0_DLL_ARPI5); in mtk_ddr3_init()
339 writel(0x80666008, priv->ddrphy + DDRPHY_B1_DLL_ARPI5); in mtk_ddr3_init()
340 writel(0x0, priv->ddrphy + DDRPHY_CA_DLL_ARPI0); in mtk_ddr3_init()
341 writel(0x0, priv->ddrphy + DDRPHY_B0_DLL_ARPI0); in mtk_ddr3_init()
342 writel(0x0, priv->ddrphy + DDRPHY_B1_DLL_ARPI0); in mtk_ddr3_init()
343 writel(0x400, priv->ddrphy + DDRPHY_CA_DLL_ARPI2); in mtk_ddr3_init()
344 writel(0x20400, priv->ddrphy + DDRPHY_B0_DLL_ARPI2); in mtk_ddr3_init()
345 writel(0x20400, priv->ddrphy + DDRPHY_B1_DLL_ARPI2); in mtk_ddr3_init()
346 writel(0x0, priv->ddrphy + DDRPHY_SHU1_PLL9); in mtk_ddr3_init()
347 writel(0x0, priv->ddrphy + DDRPHY_SHU1_PLL11); in mtk_ddr3_init()
348 writel(0xf7f, priv->ddrphy + DDRPHY_SHU1_PLL0); in mtk_ddr3_init()
349 writel(0x40000, priv->ddrphy + DDRPHY_SHU1_PLL8); in mtk_ddr3_init()
350 writel(0x40000, priv->ddrphy + DDRPHY_SHU1_PLL10); in mtk_ddr3_init()
351 writel(0xe57800fe, priv->ddrphy + DDRPHY_SHU1_PLL4); in mtk_ddr3_init()
352 writel(0xe57800fe, priv->ddrphy + DDRPHY_SHU1_PLL6); in mtk_ddr3_init()
354 writel(0xB5000000, priv->ddrphy + DDRPHY_SHU1_PLL5); in mtk_ddr3_init()
355 writel(0xB5000000, priv->ddrphy + DDRPHY_SHU1_PLL7); in mtk_ddr3_init()
357 writel(0x14d0002, priv->ddrphy + DDRPHY_PLL5); in mtk_ddr3_init()
358 writel(0x14d0002, priv->ddrphy + DDRPHY_PLL7); in mtk_ddr3_init()
359 writel(0x80040000, priv->ddrphy + DDRPHY_SHU1_PLL8); in mtk_ddr3_init()
360 writel(0x80040000, priv->ddrphy + DDRPHY_SHU1_PLL10); in mtk_ddr3_init()
361 writel(0xf, priv->ddrphy + DDRPHY_SHU1_PLL1); in mtk_ddr3_init()
362 writel(0x4, priv->ddrphy + DDRPHY_CA_DLL_ARPI0); in mtk_ddr3_init()
363 writel(0x1, priv->ddrphy + DDRPHY_B0_DLL_ARPI0); in mtk_ddr3_init()
364 writel(0x1, priv->ddrphy + DDRPHY_B1_DLL_ARPI0); in mtk_ddr3_init()
365 writel(0x698600, priv->ddrphy + DDRPHY_CA_DLL_ARPI5); in mtk_ddr3_init()
366 writel(0xc0778600, priv->ddrphy + DDRPHY_B0_DLL_ARPI5); in mtk_ddr3_init()
367 writel(0xc0778600, priv->ddrphy + DDRPHY_B1_DLL_ARPI5); in mtk_ddr3_init()
368 writel(0x0, priv->ddrphy + DDRPHY_CA_DLL_ARPI4); in mtk_ddr3_init()
369 writel(0x0, priv->ddrphy + DDRPHY_B0_DLL_ARPI4); in mtk_ddr3_init()
370 writel(0x0, priv->ddrphy + DDRPHY_B1_DLL_ARPI4); in mtk_ddr3_init()
371 writel(0x2ba800, priv->ddrphy + DDRPHY_CA_DLL_ARPI1); in mtk_ddr3_init()
372 writel(0x2ae806, priv->ddrphy + DDRPHY_B0_DLL_ARPI1); in mtk_ddr3_init()
373 writel(0xae806, priv->ddrphy + DDRPHY_B1_DLL_ARPI1); in mtk_ddr3_init()
374 writel(0xba000, priv->ddrphy + DDRPHY_CA_DLL_ARPI3); in mtk_ddr3_init()
375 writel(0x2e800, priv->ddrphy + DDRPHY_B0_DLL_ARPI3); in mtk_ddr3_init()
376 writel(0x2e800, priv->ddrphy + DDRPHY_B1_DLL_ARPI3); in mtk_ddr3_init()
377 writel(0x0, priv->ddrphy + DDRPHY_SHU1_CA_CMD4); in mtk_ddr3_init()
378 writel(0x0, priv->ddrphy + DDRPHY_SHU1_B0_DQ4); in mtk_ddr3_init()
379 writel(0x0, priv->ddrphy + DDRPHY_SHU1_B1_DQ4); in mtk_ddr3_init()
380 writel(0x4, priv->ddrphy + DDRPHY_CA_DLL_ARPI0); in mtk_ddr3_init()
381 writel(0x1, priv->ddrphy + DDRPHY_B0_DLL_ARPI0); in mtk_ddr3_init()
382 writel(0x1, priv->ddrphy + DDRPHY_B1_DLL_ARPI0); in mtk_ddr3_init()
383 writel(0x32cf0000, priv->ddrphy + DDRPHY_SHU1_CA_CMD6); in mtk_ddr3_init()
384 writel(0x32cd0000, priv->ddrphy + DDRPHY_SHU1_B0_DQ6); in mtk_ddr3_init()
385 writel(0x32cd0000, priv->ddrphy + DDRPHY_SHU1_B1_DQ6); in mtk_ddr3_init()
386 writel(0x80010000, priv->ddrphy + DDRPHY_PLL1); in mtk_ddr3_init()
387 writel(0x80000000, priv->ddrphy + DDRPHY_PLL2); in mtk_ddr3_init()
390 writel(0xc, priv->ddrphy + DDRPHY_CA_DLL_ARPI0); in mtk_ddr3_init()
391 writel(0x9, priv->ddrphy + DDRPHY_B0_DLL_ARPI0); in mtk_ddr3_init()
392 writel(0x9, priv->ddrphy + DDRPHY_B1_DLL_ARPI0); in mtk_ddr3_init()
393 writel(0xd0000, priv->ddrphy + DDRPHY_PLL4); in mtk_ddr3_init()
396 writel(0x82, priv->ddrphy + DDRPHY_MISC_CTRL1); in mtk_ddr3_init()
397 writel(0x2, priv->dramc_ao + DRAMC_DDRCONF0); in mtk_ddr3_init()
398 writel(0x3acf0000, priv->ddrphy + DDRPHY_SHU1_CA_CMD6); in mtk_ddr3_init()
399 writel(0x3acd0000, priv->ddrphy + DDRPHY_SHU1_B0_DQ6); in mtk_ddr3_init()
400 writel(0x3acd0000, priv->ddrphy + DDRPHY_SHU1_B1_DQ6); in mtk_ddr3_init()
403 writel(0x0, priv->ddrphy + DDRPHY_CA_DLL_ARPI2); in mtk_ddr3_init()
404 writel(0x0, priv->ddrphy + DDRPHY_B0_DLL_ARPI2); in mtk_ddr3_init()
405 writel(0x0, priv->ddrphy + DDRPHY_B1_DLL_ARPI2); in mtk_ddr3_init()
406 writel(0x80, priv->ddrphy + DDRPHY_MISC_CTRL1); in mtk_ddr3_init()
407 writel(0x0, priv->dramc_ao + DRAMC_DDRCONF0); in mtk_ddr3_init()
408 writel(0x80000000, priv->ddrphy + DDRPHY_PLL1); in mtk_ddr3_init()
411 writel(0x698e00, priv->ddrphy + DDRPHY_CA_DLL_ARPI5); in mtk_ddr3_init()
414 writel(0xc0778e00, priv->ddrphy + DDRPHY_B0_DLL_ARPI5); in mtk_ddr3_init()
417 writel(0xc0778e00, priv->ddrphy + DDRPHY_B1_DLL_ARPI5); in mtk_ddr3_init()
425 writel(0x51e, priv->ddrphy + DDRPHY_B0_DQ3); in mtk_ddr3_init()
426 writel(0x51e, priv->ddrphy + DDRPHY_B1_DQ3); in mtk_ddr3_init()
427 writel(0x8100008c, priv->ddrphy + DDRPHY_MISC_CTRL1); in mtk_ddr3_init()
428 writel(0x80101, priv->ddrphy + DDRPHY_CA_CMD8); in mtk_ddr3_init()
429 writel(0x100, priv->ddrphy + DDRPHY_CA_CMD7); in mtk_ddr3_init()
430 writel(0x0, priv->ddrphy + DDRPHY_CA_CMD7); in mtk_ddr3_init()
431 writel(0x0, priv->ddrphy + DDRPHY_B0_DQ7); in mtk_ddr3_init()
432 writel(0x0, priv->ddrphy + DDRPHY_B1_DQ7); in mtk_ddr3_init()
433 writel(0x51e, priv->ddrphy + DDRPHY_B0_DQ3); in mtk_ddr3_init()
434 writel(0xff051e, priv->ddrphy + DDRPHY_B1_DQ3); in mtk_ddr3_init()
435 writel(0x0, priv->ddrphy + DDRPHY_B0_DQ2); in mtk_ddr3_init()
436 writel(0x1ff, priv->ddrphy + DDRPHY_B1_DQ2); in mtk_ddr3_init()
439 writel(0x5fc, priv->ddrphy + DDRPHY_B0_DQ3); in mtk_ddr3_init()
440 writel(0xff05fc, priv->ddrphy + DDRPHY_B1_DQ3); in mtk_ddr3_init()
441 writel(0x10c12d9, priv->ddrphy + DDRPHY_B0_DQ6); in mtk_ddr3_init()
442 writel(0x10c12d9, priv->ddrphy + DDRPHY_B1_DQ6); in mtk_ddr3_init()
443 writel(0xc0259, priv->ddrphy + DDRPHY_CA_CMD6); in mtk_ddr3_init()
444 writel(0x4000, priv->ddrphy + DDRPHY_B0_DQ2); in mtk_ddr3_init()
445 writel(0x41ff, priv->ddrphy + DDRPHY_B1_DQ2); in mtk_ddr3_init()
446 writel(0x0, priv->ddrphy + DDRPHY_B0_DQ8); in mtk_ddr3_init()
447 writel(0x100, priv->ddrphy + DDRPHY_B1_DQ8); in mtk_ddr3_init()
448 writel(0x3110e0e, priv->ddrphy + DDRPHY_B0_DQ5); in mtk_ddr3_init()
449 writel(0x3110e0e, priv->ddrphy + DDRPHY_B1_DQ5); in mtk_ddr3_init()
450 writel(0x51060e, priv->ddrphy + DDRPHY_SHU1_B0_DQ5); in mtk_ddr3_init()
451 writel(0x51060e, priv->ddrphy + DDRPHY_SHU1_B1_DQ5); in mtk_ddr3_init()
452 writel(0x39eff6, priv->dramc_ao + DRAMC_SHU_SCINTV); in mtk_ddr3_init()
453 writel(0x204ffff, priv->dramc_ao + DRAMC_CLKAR); in mtk_ddr3_init()
454 writel(0x31b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL); in mtk_ddr3_init()
455 writel(0x0, priv->dramc_ao + DRAMC_PERFCTL0); in mtk_ddr3_init()
456 writel(0x80000, priv->dramc_ao + DRAMC_PERFCTL0); in mtk_ddr3_init()
459 writel(0x65714001, priv->dramc_ao + DRAMC_REFCTRL0); in mtk_ddr3_init()
461 writel(0x11351131, priv->ddrphy + DDRPHY_MISC_CTRL3); in mtk_ddr3_init()
462 writel(0x200600, priv->dramc_ao + DRAMC_SHU_DQSG_RETRY); in mtk_ddr3_init()
463 writel(0x101d007, priv->dramc_ao + DRAMC_SHUCTRL2); in mtk_ddr3_init()
464 writel(0xe090601, priv->dramc_ao + DRAMC_DVFSDLL); in mtk_ddr3_init()
465 writel(0x20003000, priv->dramc_ao + DRAMC_DDRCONF0); in mtk_ddr3_init()
466 writel(0x3900020f, priv->ddrphy + DDRPHY_MISC_CTRL0); in mtk_ddr3_init()
467 writel(0xa20810bf, priv->dramc_ao + DRAMC_SHU_CONF0); in mtk_ddr3_init()
468 writel(0x30050, priv->dramc_ao + DRAMC_SHU_ODTCTRL); in mtk_ddr3_init()
469 writel(0x25712000, priv->dramc_ao + DRAMC_REFCTRL0); in mtk_ddr3_init()
470 writel(0xb0100000, priv->dramc_ao + DRAMC_STBCAL); in mtk_ddr3_init()
471 writel(0x8000000, priv->dramc_ao + DRAMC_SREFCTRL); in mtk_ddr3_init()
472 writel(0xc0000000, priv->dramc_ao + DRAMC_SHU_PIPE); in mtk_ddr3_init()
473 writel(0x731004, priv->dramc_ao + DRAMC_RKCFG); in mtk_ddr3_init()
474 writel(0x8007320f, priv->dramc_ao + DRAMC_SHU_CONF2); in mtk_ddr3_init()
475 writel(0x2a7c0, priv->dramc_ao + DRAMC_SHU_SCINTV); in mtk_ddr3_init()
476 writel(0xc110, priv->dramc_ao + DRAMC_SHUCTRL); in mtk_ddr3_init()
477 writel(0x30000700, priv->dramc_ao + DRAMC_REFCTRL1); in mtk_ddr3_init()
478 writel(0x6543b321, priv->dramc_ao + DRAMC_REFRATRE_FILTER); in mtk_ddr3_init()
481 writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA1); in mtk_ddr3_init()
482 writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA2); in mtk_ddr3_init()
483 writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA3); in mtk_ddr3_init()
484 writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA4); in mtk_ddr3_init()
485 writel(0x10000111, priv->dramc_ao + DRAMC_SHU_SELPH_CA5); in mtk_ddr3_init()
486 writel(0x1000000, priv->dramc_ao + DRAMC_SHU_SELPH_CA6); in mtk_ddr3_init()
487 writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA7); in mtk_ddr3_init()
488 writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA8); in mtk_ddr3_init()
489 writel(0x0, priv->ddrphy + DDRPHY_SHU1_R0_CA_CMD9); in mtk_ddr3_init()
490 writel(0x0, priv->ddrphy + DDRPHY_SHU1_R1_CA_CMD9); in mtk_ddr3_init()
491 writel(0x11112222, priv->dramc_ao + DRAMC_SHU_SELPH_DQS0); in mtk_ddr3_init()
492 writel(0x33331111, priv->dramc_ao + DRAMC_SHU_SELPH_DQS1); in mtk_ddr3_init()
493 writel(0x11112222, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ0); in mtk_ddr3_init()
494 writel(0x11112222, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ1); in mtk_ddr3_init()
495 writel(0x33331111, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ2); in mtk_ddr3_init()
496 writel(0x33331111, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ3); in mtk_ddr3_init()
497 writel(0x11112222, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQ0); in mtk_ddr3_init()
498 writel(0x11112222, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQ1); in mtk_ddr3_init()
499 writel(0x33331111, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQ2); in mtk_ddr3_init()
500 writel(0x33331111, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQ3); in mtk_ddr3_init()
501 writel(0xf0f00, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ7); in mtk_ddr3_init()
502 writel(0xf0f00, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ7); in mtk_ddr3_init()
503 writel(0xf0f00, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ7); in mtk_ddr3_init()
504 writel(0xf0f00, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ7); in mtk_ddr3_init()
505 writel(0x0, priv->dramc_ao + DRAMC_SHURK0_SELPH_ODTEN0); in mtk_ddr3_init()
506 writel(0x0, priv->dramc_ao + DRAMC_SHURK0_SELPH_ODTEN1); in mtk_ddr3_init()
507 writel(0x0, priv->dramc_ao + DRAMC_SHURK1_SELPH_ODTEN0); in mtk_ddr3_init()
508 writel(0x0, priv->dramc_ao + DRAMC_SHURK1_SELPH_ODTEN1); in mtk_ddr3_init()
509 writel(0x0, priv->dramc_ao + DRAMC_SHURK2_SELPH_ODTEN0); in mtk_ddr3_init()
510 writel(0x66666666, priv->dramc_ao + DRAMC_SHURK2_SELPH_ODTEN1); in mtk_ddr3_init()
511 writel(0x2c000b0f, priv->dramc_ao + DRAMC_SHU_CONF1); in mtk_ddr3_init()
512 writel(0x11111111, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQSG0); in mtk_ddr3_init()
513 writel(0x64646464, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQSG1); in mtk_ddr3_init()
514 writel(0x11111111, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQSG0); in mtk_ddr3_init()
515 writel(0x64646464, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQSG1); in mtk_ddr3_init()
516 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ2); in mtk_ddr3_init()
517 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ3); in mtk_ddr3_init()
518 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ4); in mtk_ddr3_init()
519 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ5); in mtk_ddr3_init()
520 writel(0x0, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ6); in mtk_ddr3_init()
521 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ2); in mtk_ddr3_init()
522 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ3); in mtk_ddr3_init()
523 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ4); in mtk_ddr3_init()
524 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ5); in mtk_ddr3_init()
525 writel(0x0, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ6); in mtk_ddr3_init()
526 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ2); in mtk_ddr3_init()
527 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ3); in mtk_ddr3_init()
528 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ4); in mtk_ddr3_init()
529 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ5); in mtk_ddr3_init()
530 writel(0x0, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ6); in mtk_ddr3_init()
531 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ2); in mtk_ddr3_init()
532 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ3); in mtk_ddr3_init()
533 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ4); in mtk_ddr3_init()
534 writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ5); in mtk_ddr3_init()
535 writel(0x0, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ6); in mtk_ddr3_init()
536 writel(0x20000001, priv->dramc_ao + DRAMC_SHU_RANKCTL); in mtk_ddr3_init()
537 writel(0x2, priv->dramc_ao + DRAMC_SHURK0_DQSCTL); in mtk_ddr3_init()
538 writel(0x2, priv->dramc_ao + DRAMC_SHURK1_DQSCTL); in mtk_ddr3_init()
539 writel(0x4020b07, priv->dramc_ao + DRAMC_SHU_ACTIM0); in mtk_ddr3_init()
540 writel(0xb060400, priv->dramc_ao + DRAMC_SHU_ACTIM1); in mtk_ddr3_init()
541 writel(0x8090200, priv->dramc_ao + DRAMC_SHU_ACTIM2); in mtk_ddr3_init()
542 writel(0x810018, priv->dramc_ao + DRAMC_SHU_ACTIM3); in mtk_ddr3_init()
543 writel(0x1e9700ff, priv->dramc_ao + DRAMC_SHU_ACTIM4); in mtk_ddr3_init()
544 writel(0x1000908, priv->dramc_ao + DRAMC_SHU_ACTIM5); in mtk_ddr3_init()
545 writel(0x801040b, priv->dramc_ao + DRAMC_SHU_ACTIM_XRT); in mtk_ddr3_init()
546 writel(0x20000D1, priv->dramc_ao + DRAMC_SHU_AC_TIME_05T); in mtk_ddr3_init()
547 writel(0x80010000, priv->ddrphy + DDRPHY_PLL2); in mtk_ddr3_init()
550 writel(0x81080000, priv->dramc_ao + DRAMC_MISCTL0); in mtk_ddr3_init()
551 writel(0xacf13, priv->dramc_ao + DRAMC_PERFCTL0); in mtk_ddr3_init()
552 writel(0xacf12, priv->dramc_ao + DRAMC_PERFCTL0); in mtk_ddr3_init()
553 writel(0x80, priv->dramc_ao + DRAMC_ARBCTL); in mtk_ddr3_init()
554 writel(0x9, priv->dramc_ao + DRAMC_PADCTRL); in mtk_ddr3_init()
555 writel(0x80000107, priv->dramc_ao + DRAMC_DRAMC_PD_CTRL); in mtk_ddr3_init()
556 writel(0x3000000c, priv->dramc_ao + DRAMC_CLKCTRL); in mtk_ddr3_init()
557 writel(0x25714001, priv->dramc_ao + DRAMC_REFCTRL0); in mtk_ddr3_init()
558 writel(0x35b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL); in mtk_ddr3_init()
559 writel(0x4300000, priv->dramc_ao + DRAMC_CATRAINING1); in mtk_ddr3_init()
560 writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL); in mtk_ddr3_init()
561 writel(0x731414, priv->dramc_ao + DRAMC_RKCFG); in mtk_ddr3_init()
562 writel(0x733414, priv->dramc_ao + DRAMC_RKCFG); in mtk_ddr3_init()
565 writel(0x80002050, priv->dramc_ao + DRAMC_CKECTRL); in mtk_ddr3_init()
568 writel(0x400000, priv->dramc_ao + DRAMC_MRS); in mtk_ddr3_init()
569 writel(0x401800, priv->dramc_ao + DRAMC_MRS); in mtk_ddr3_init()
570 writel(0x1, priv->dramc_ao + DRAMC_SPCMD); in mtk_ddr3_init()
571 writel(0x0, priv->dramc_ao + DRAMC_SPCMD); in mtk_ddr3_init()
574 writel(0x601800, priv->dramc_ao + DRAMC_MRS); in mtk_ddr3_init()
575 writel(0x600000, priv->dramc_ao + DRAMC_MRS); in mtk_ddr3_init()
576 writel(0x1, priv->dramc_ao + DRAMC_SPCMD); in mtk_ddr3_init()
577 writel(0x0, priv->dramc_ao + DRAMC_SPCMD); in mtk_ddr3_init()
580 writel(0x200000, priv->dramc_ao + DRAMC_MRS); in mtk_ddr3_init()
581 writel(0x200400, priv->dramc_ao + DRAMC_MRS); in mtk_ddr3_init()
582 writel(0x1, priv->dramc_ao + DRAMC_SPCMD); in mtk_ddr3_init()
583 writel(0x0, priv->dramc_ao + DRAMC_SPCMD); in mtk_ddr3_init()
586 writel(0x400, priv->dramc_ao + DRAMC_MRS); in mtk_ddr3_init()
587 writel(0x1d7000, priv->dramc_ao + DRAMC_MRS); in mtk_ddr3_init()
588 writel(0x1, priv->dramc_ao + DRAMC_SPCMD); in mtk_ddr3_init()
589 writel(0x0, priv->dramc_ao + DRAMC_SPCMD); in mtk_ddr3_init()
592 writel(0x702201, priv->dramc_ao + DRAMC_DRAMCTRL); in mtk_ddr3_init()
593 writel(0x10, priv->dramc_ao + DRAMC_SPCMD); in mtk_ddr3_init()
594 writel(0x0, priv->dramc_ao + DRAMC_SPCMD); in mtk_ddr3_init()
595 writel(0x20, priv->dramc_ao + DRAMC_SPCMD); in mtk_ddr3_init()
596 writel(0x0, priv->dramc_ao + DRAMC_SPCMD); in mtk_ddr3_init()
597 writel(0x1, priv->dramc_ao + DRAMC_HW_MRR_FUN); in mtk_ddr3_init()
598 writel(0x702301, priv->dramc_ao + DRAMC_DRAMCTRL); in mtk_ddr3_init()
599 writel(0x702301, priv->dramc_ao + DRAMC_DRAMCTRL); in mtk_ddr3_init()
600 writel(0xa56, priv->dramc_ao + DRAMC_ZQCS); in mtk_ddr3_init()
601 writel(0xff0000, priv->dramc_ao + DRAMC_SHU_CONF3); in mtk_ddr3_init()
602 writel(0x15b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL); in mtk_ddr3_init()
603 writel(0x2cb00b0f, priv->dramc_ao + DRAMC_SHU_CONF1); in mtk_ddr3_init()
604 writel(0x65714001, priv->dramc_ao + DRAMC_REFCTRL0); in mtk_ddr3_init()
605 writel(0x48000000, priv->dramc_ao + DRAMC_SREFCTRL); in mtk_ddr3_init()
606 writel(0xc0000107, priv->dramc_ao + DRAMC_DRAMC_PD_CTRL); in mtk_ddr3_init()
607 writel(0x10002, priv->dramc_ao + DRAMC_EYESCAN); in mtk_ddr3_init()
608 writel(0x15e00, priv->dramc_ao + DRAMC_STBCAL1); in mtk_ddr3_init()
609 writel(0x100000, priv->dramc_ao + DRAMC_TEST2_1); in mtk_ddr3_init()
610 writel(0x4000, priv->dramc_ao + DRAMC_TEST2_2); in mtk_ddr3_init()
611 writel(0x12000480, priv->dramc_ao + DRAMC_TEST2_3); in mtk_ddr3_init()
612 writel(0x301d007, priv->dramc_ao + DRAMC_SHUCTRL2); in mtk_ddr3_init()
613 writel(0x4782321, priv->dramc_ao + DRAMC_DRAMCTRL); in mtk_ddr3_init()
614 writel(0x30210000, priv->dramc_ao + DRAMC_SHU_CKECTRL); in mtk_ddr3_init()
615 writel(0x20000, priv->dramc_ao + DRAMC_DUMMY_RD); in mtk_ddr3_init()
616 writel(0x4080110d, priv->dramc_ao + DRAMC_TEST2_4); in mtk_ddr3_init()
617 writel(0x30000721, priv->dramc_ao + DRAMC_REFCTRL1); in mtk_ddr3_init()
618 writel(0x0, priv->dramc_ao + DRAMC_RSTMASK); in mtk_ddr3_init()
619 writel(0x4782320, priv->dramc_ao + DRAMC_DRAMCTRL); in mtk_ddr3_init()
620 writel(0x80002000, priv->dramc_ao + DRAMC_CKECTRL); in mtk_ddr3_init()
621 writel(0x45714001, priv->dramc_ao + DRAMC_REFCTRL0); in mtk_ddr3_init()
624 writel(0x120, priv->dramc_ao + DRAMC_DRAMC_PD_CTRL); in mtk_ddr3_init()
625 writel(0x11351131, priv->ddrphy + DDRPHY_MISC_CTRL3); in mtk_ddr3_init()
626 writel(0xffffffff, priv->ddrphy + DDRPHY_MISC_CG_CTRL0); in mtk_ddr3_init()
627 writel(0x2a7fe, priv->dramc_ao + DRAMC_SHU_SCINTV); in mtk_ddr3_init()
628 writel(0xff01ff, priv->dramc_ao + DRAMC_SHU_CONF3); in mtk_ddr3_init()
629 writel(0x4782320, priv->dramc_ao + DRAMC_DRAMCTRL); in mtk_ddr3_init()
630 writel(0xa56, priv->dramc_ao + DRAMC_ZQCS); in mtk_ddr3_init()
631 writel(0x80000000, priv->dramc_ao + DRAMC_SHU1_WODT); in mtk_ddr3_init()
632 writel(0x21, priv->ddrphy + DDRPHY_SHU1_B0_DQ7); in mtk_ddr3_init()
633 writel(0x1, priv->ddrphy + DDRPHY_SHU1_B1_DQ7); in mtk_ddr3_init()
634 writel(0x35b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL); in mtk_ddr3_init()
635 writel(0x35b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL); in mtk_ddr3_init()
636 writel(0x35b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL); in mtk_ddr3_init()
637 writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL); in mtk_ddr3_init()
638 writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL); in mtk_ddr3_init()
639 writel(0x10002, priv->dramc_ao + DRAMC_EYESCAN); in mtk_ddr3_init()
640 writel(0x8100008c, priv->ddrphy + DDRPHY_MISC_CTRL1); in mtk_ddr3_init()
641 writel(0x45714001, priv->dramc_ao + DRAMC_REFCTRL0); in mtk_ddr3_init()
642 writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL); in mtk_ddr3_init()
643 writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL); in mtk_ddr3_init()
646 writel(0x1f2e2e00, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ7); in mtk_ddr3_init()
647 writel(0x202f2f00, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ7); in mtk_ddr3_init()
648 writel(0x33221100, priv->dramc_ao + DRAMC_SHU_SELPH_DQS1); in mtk_ddr3_init()
649 writel(0x11112222, priv->dramc_ao + DRAMC_SHU_SELPH_DQS0); in mtk_ddr3_init()
652 writel(0x11111010, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQSG0); in mtk_ddr3_init()
653 writel(0x20201717, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQSG1); in mtk_ddr3_init()
654 writel(0x1d1f, priv->dramc_ao + DRAMC_SHURK0_DQSIEN); in mtk_ddr3_init()
657 writel(0x03030404, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ2); in mtk_ddr3_init()
658 writel(0x01010303, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ3); in mtk_ddr3_init()
659 writel(0x01010303, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ4); in mtk_ddr3_init()
660 writel(0x01010000, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ5); in mtk_ddr3_init()
661 writel(0x03030606, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ2); in mtk_ddr3_init()
662 writel(0x02020202, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ3); in mtk_ddr3_init()
663 writel(0x04040303, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ4); in mtk_ddr3_init()
664 writel(0x06060101, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ5); in mtk_ddr3_init()
667 writel(0x28b00a0e, priv->dramc_ao + DRAMC_SHU_CONF1); in mtk_ddr3_init()
670 writel(0x11112222, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ0); in mtk_ddr3_init()
671 writel(0x22220000, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ2); in mtk_ddr3_init()
672 writel(0x11112222, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ1); in mtk_ddr3_init()
673 writel(0x22220000, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ3); in mtk_ddr3_init()
674 writel(0x1f2e2e00, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ7); in mtk_ddr3_init()
675 writel(0x202f2f00, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ7); in mtk_ddr3_init()
685 priv->emi = dev_read_addr_index(dev, 0); in mtk_ddr3_probe()
700 ret = clk_get_by_index(dev, 0, &priv->phy); in mtk_ddr3_probe()
720 return 0; in mtk_ddr3_probe()
731 case 0: in mtk_ddr3_get_info()
747 return 0; in mtk_ddr3_get_info()